1 /*
2 * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
3 * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved.
4 * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #include <common/debug.h>
10 #include <common/runtime_svc.h>
11 #include <def.h>
12 #include <drivers/generic_delay_timer.h>
13 #include <lib/mmio.h>
14 #include <lib/xlat_tables/xlat_tables_v2.h>
15 #include <plat/common/platform.h>
16 #include <plat_clkfunc.h>
17 #include <plat_common.h>
18 #include <plat_ipi.h>
19 #include <plat_private.h>
20
21 uint32_t platform_id, platform_version, rtlversion, psversion, pmcversion;
22
23 /*
24 * Table of regions to map using the MMU.
25 * This doesn't include TZRAM as the 'mem_layout' argument passed to
26 * configure_mmu_elx() will give the available subset of that,
27 */
28 const mmap_region_t plat_mmap[] = {
29 MAP_REGION_FLAT(DEVICE0_BASE, DEVICE0_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
30 MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
31 MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
32 MAP_REGION_FLAT(CRF_BASE, CRF_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
33 MAP_REGION_FLAT(IPI_BASE, IPI_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
34 #if TRANSFER_LIST
35 MAP_REGION_FLAT(FW_HANDOFF_BASE, FW_HANDOFF_BASE + FW_HANDOFF_SIZE,
36 MT_MEMORY | MT_RW | MT_NS),
37 #endif
38 { 0 }
39 };
40
plat_get_mmap(void)41 const mmap_region_t *plat_get_mmap(void)
42 {
43 return plat_mmap;
44 }
45
46 /* For saving cpu clock for certain platform */
47 uint32_t cpu_clock;
48
board_name_decode(void)49 const char *board_name_decode(void)
50 {
51 const char *platform;
52
53 switch (platform_id) {
54 case SPP:
55 platform = "IPP";
56 break;
57 case EMU:
58 platform = "EMU";
59 break;
60 case SILICON:
61 platform = "Silicon";
62 break;
63 case QEMU:
64 platform = "QEMU";
65 break;
66 default:
67 platform = "Unknown";
68 }
69
70 return platform;
71 }
72
board_detection(void)73 void board_detection(void)
74 {
75 uint32_t version_type;
76
77 version_type = mmio_read_32(PMC_TAP_VERSION);
78 platform_id = FIELD_GET((uint32_t)PLATFORM_MASK, version_type);
79 platform_version = FIELD_GET((uint32_t)PLATFORM_VERSION_MASK, version_type);
80 rtlversion = FIELD_GET((uint32_t)RTL_VERSION, version_type);
81 psversion = FIELD_GET((uint32_t)PS_VERSION, version_type);
82 pmcversion = FIELD_GET((uint32_t)PMC_VERSION, version_type);
83
84 if (platform_id == QEMU_COSIM) {
85 platform_id = QEMU;
86 }
87
88 /* Make sure that console is setup to see this message */
89 VERBOSE("Platform id: %d version: %d.%d\n", platform_id,
90 platform_version / 10U, platform_version % 10U);
91 }
92
get_uart_clk(void)93 uint32_t get_uart_clk(void)
94 {
95 uint32_t uart_clock = 0;
96
97 switch (platform_id) {
98 case SPP:
99 case SPP_MMD:
100 uart_clock = cpu_clock;
101 break;
102 case EMU:
103 case EMU_MMD:
104 uart_clock = 25000000;
105 break;
106 case QEMU:
107 /* Random values now */
108 uart_clock = 25000000;
109 break;
110 case SILICON:
111 uart_clock = 100000000;
112 break;
113 default:
114 panic();
115 }
116
117 return uart_clock;
118 }
119
config_setup(void)120 void config_setup(void)
121 {
122 uint32_t val;
123 uintptr_t crl_base, iou_scntrs_base, psx_base;
124
125 crl_base = CRL;
126 iou_scntrs_base = IOU_SCNTRS_BASE;
127 psx_base = PSX_CRF;
128
129 /* Reset for system timestamp generator in FPX */
130 mmio_write_32(psx_base + PSX_CRF_RST_TIMESTAMP_OFFSET, 0);
131
132 /* Global timer init - Program time stamp reference clk */
133 val = mmio_read_32(crl_base + CRL_TIMESTAMP_REF_CTRL_OFFSET);
134 val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT;
135 mmio_write_32(crl_base + CRL_TIMESTAMP_REF_CTRL_OFFSET, val);
136
137 /* Clear reset of timestamp reg */
138 mmio_write_32(crl_base + CRL_RST_TIMESTAMP_OFFSET, 0);
139
140 /* Program freq register in System counter and enable system counter. */
141 mmio_write_32(iou_scntrs_base + IOU_SCNTRS_BASE_FREQ_OFFSET,
142 cpu_clock);
143 mmio_write_32(iou_scntrs_base + IOU_SCNTRS_COUNTER_CONTROL_REG_OFFSET,
144 IOU_SCNTRS_CONTROL_EN);
145
146 /* set cntfrq_el0 value so that software can discover the frequency of the system counter */
147 set_cnt_freq();
148
149 generic_delay_timer_init();
150
151 /* Configure IPI data */
152 soc_ipi_config_table_init();
153 }
154