Merge changes from topic "sbsa2" into integration

* changes:
feat(qemu): skip paged image info
feat(optee): check paged image size
feat(qemu-sbsa): support s-el2 and s-el1 spmc

feat(qemu-sbsa): support s-el2 and s-el1 spmc

Reserve memory for TB_FW_CONFIG and TOS_FW_CONFIG if configured with
SPD=spmd and optionally SPMD_SPM_AT_SEL2=1.

Change-Id: I2f27502b6d5f9f0131ab8ba273

feat(qemu-sbsa): support s-el2 and s-el1 spmc

Reserve memory for TB_FW_CONFIG and TOS_FW_CONFIG if configured with
SPD=spmd and optionally SPMD_SPM_AT_SEL2=1.

Change-Id: I2f27502b6d5f9f0131ab8ba273ab738de5643d45
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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Merge "feat(qemu): add hob support for qemu platforms" into integration

Merge changes from topic "memory_bank" into integration

* changes:
fix(qemu): statically allocate bitlocks array
feat(qemu): update for renamed struct memory_bank
feat(fvp): increase GPT PPS t

Merge changes from topic "memory_bank" into integration

* changes:
fix(qemu): statically allocate bitlocks array
feat(qemu): update for renamed struct memory_bank
feat(fvp): increase GPT PPS to 1TB
feat(gpt): statically allocate bitlocks array
chore(gpt): define PPS in platform header files
feat(fvp): allocate L0 GPT at the top of SRAM
feat(fvp): change size of PCIe memory region 2
feat(rmm): add PCIe IO info to Boot manifest
feat(fvp): define single Root region

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fix(qemu): statically allocate bitlocks array

gpt_runtime_init() now takes the bitlock array's address and size as
argument. Rather than reserving space at the end of the L0 GPT for
storing bitlocks

fix(qemu): statically allocate bitlocks array

gpt_runtime_init() now takes the bitlock array's address and size as
argument. Rather than reserving space at the end of the L0 GPT for
storing bitlocks, allocate a static array and pass its address to
gpt_runtime_init(). This frees up a little bit of space formerly
reserved for alignment of the GPT.

Change-Id: I48a1a2bc230f64e13e3ed08b18ebdc2d387d77d0
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>

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feat(qemu): add hob support for qemu platforms

This change introduces the hob support for both qemu platforms (virt and
sbsa).

As the hob list feature relies on transfer list, the transfer list
sup

feat(qemu): add hob support for qemu platforms

This change introduces the hob support for both qemu platforms (virt and
sbsa).

As the hob list feature relies on transfer list, the transfer list
support is promoted to common qemu build configuration. The platforms
specific definitions are updated accordingly.

Change-Id: I473d83388fe95408d34515bf7bcbdd64ce4e777d
Signed-off-by: Kun Qin <kuqin@microsoft.com>

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Merge changes from topic "gerrit-master-v3" into integration

* changes:
feat(qemu-sbsa): add support for RME on SBSA machine
feat(qemu-sbsa): configure RMM manifest based on system RAM
feat(qe

Merge changes from topic "gerrit-master-v3" into integration

* changes:
feat(qemu-sbsa): add support for RME on SBSA machine
feat(qemu-sbsa): configure RMM manifest based on system RAM
feat(qemu-sbsa): configure GPT based on system RAM
feat(qemu-sbsa): adjust DT memory start address when supporting RME
feat(qemu-sbsa): relocate DT after the RMM when RME is enabled
feat(qemu-sbsa): dissociate QEMU NS start address and NS_DRAM0_BASE
feat(qemu-sbsa): increase maximum FIP size
refactor(qemu-sbsa): move all DT related functions to sbsa_platform.c
refactor(qemu-sbsa): create accessor functions for platform info
refactor(qemu-sbsa): rename function sip_svc_init() to something more meaningful
refactor(qemu-sbsa): move DT related structures to their own header
refactor(qemu-sbsa): rename struct dynamic_platform_info
refactor(qemu): make L0GPT size configurable
refactor(qemu): move GPT setup to BL31
fix(qemu-sbsa): fix compilation error when accessing DT functions

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feat(qemu-sbsa): add support for RME on SBSA machine

Add the necessary foundation to support Arm's RME extension on the SBSA
reference architecture.

Change-Id: If5a63ed0015cb33fcae367ff2cded811bbdc

feat(qemu-sbsa): add support for RME on SBSA machine

Add the necessary foundation to support Arm's RME extension on the SBSA
reference architecture.

Change-Id: If5a63ed0015cb33fcae367ff2cded811bbdc1e54
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>

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feat(qemu-sbsa): dissociate QEMU NS start address and NS_DRAM0_BASE

When RME is enabled the RMM is placed at the bottom of the NS RAM,
meaning that NS_DRAM0_BASE has to be located after that.

This

feat(qemu-sbsa): dissociate QEMU NS start address and NS_DRAM0_BASE

When RME is enabled the RMM is placed at the bottom of the NS RAM,
meaning that NS_DRAM0_BASE has to be located after that.

This patch disscociates the base of the NS RAM as defined by QEMU by
introducing a new define, PLAT_QEMU_DRAM0_BASE. An offset can be added
to that new define when the software's view of the base memory need to
differ from QEMU.

No change in functionality.

Change-Id: I887f9993d5a61896352cfff17e0d92e2c2b9030a
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>

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feat(qemu-sbsa): increase maximum FIP size

Following what was done for:

f465ac221001 ("fix(qemu): increase max FIP size")

increase the size of the FIP image to take up the remaining
space in FLASH

feat(qemu-sbsa): increase maximum FIP size

Following what was done for:

f465ac221001 ("fix(qemu): increase max FIP size")

increase the size of the FIP image to take up the remaining
space in FLASH0. That way the RMM image can also be added
to the FIP.

Change-Id: I89bba36f751468e99241f1c20b51c48fe06d8229
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>

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Merge "refactor(qemu): do not hardcode counter frequency" into integration

refactor(qemu): do not hardcode counter frequency

From QEMU change:

> In previous versions of the Arm architecture, the frequency of the
> generic timers as reported in CNTFRQ_EL0 could be any IMPD

refactor(qemu): do not hardcode counter frequency

From QEMU change:

> In previous versions of the Arm architecture, the frequency of the
> generic timers as reported in CNTFRQ_EL0 could be any IMPDEF value,
> and for QEMU we picked 62.5MHz, giving a timer tick period of 16ns.
> In Armv8.6, the architecture standardized this frequency to 1GHz.

This change stops TF-A from hardcoding 62.5MHz frequency. Instead value
stored in CNTFRQ_EL0 would be used. As a result we get 62.5MHz on older
cores and 1GHz on newer ones.

Change-Id: I7d414ce6d3708e598bbb5a6f79eb2d4ec8e15ac4
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

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Merge "feat(qemu-sbsa): handle memory information" into integration

feat(qemu-sbsa): handle memory information

As a part of removing DeviceTree from EDK2, we move functions to TF-A:

- counting the number of memory nodes
- checking NUMA node id
- checking the memory

feat(qemu-sbsa): handle memory information

As a part of removing DeviceTree from EDK2, we move functions to TF-A:

- counting the number of memory nodes
- checking NUMA node id
- checking the memory address

Signed-off-by: Xiong Yining <xiongyining1480@phytium.com.cn>
Signed-off-by: Chen Baozi <chenbaozi@phytium.com.cn>
Change-Id: Ib7bce3a65c817a5b3bef6c9e0a459c7ce76c7e35

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Merge "fix(qemu_sbsa): align FIP base to BL1 size" into integration

fix(qemu_sbsa): align FIP base to BL1 size

RME patch series shown that we can build larger BL1 than we can run:

NOTICE: Booting Trusted Firmware
NOTICE: BL1: v2.9(debug):v2.9.0-736-g08548888a
NOT

fix(qemu_sbsa): align FIP base to BL1 size

RME patch series shown that we can build larger BL1 than we can run:

NOTICE: Booting Trusted Firmware
NOTICE: BL1: v2.9(debug):v2.9.0-736-g08548888a
NOTICE: BL1: Built : 12:10:39, Sep 18 2023
INFO: BL1: RAM 0x3ffee000 - 0x3fffb000
INFO: BL1: Loading BL2
WARNING: Firmware Image Package header check failed.

RME pushed debug build BL1 over 0x8000 in size.
This exposed an error where FIP_BASE (supposed to be at BL1_SIZE offset
from start of flash) was actually 0x8000 and not 0x12000.
Make sure we have space for BL1 by deriving FIP_BASE from it.

Note: this is a breaking change for edk2 FD image generation, which had
similarly hardcoded a 0x8000 offset. These images must be updated in
lock-step.

Change-Id: I8a1a85e82319945a4412c424467d818d5b6e4ecd
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

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Merge changes from topic "version/0.1-gic" into integration

* changes:
feat(qemu-sbsa): handle GIC base
feat(qemu-sbsa): handle platform version

feat(qemu-sbsa): handle GIC base

QEMU provides GIC information in DeviceTree (on platform version 0.1+).
Read it and provide to next firmware level via SMC.

Signed-off-by: Marcin Juszkiewicz <marci

feat(qemu-sbsa): handle GIC base

QEMU provides GIC information in DeviceTree (on platform version 0.1+).
Read it and provide to next firmware level via SMC.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: I383919bd172acc8873292a0c5e4469651dc96fb9

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Merge changes I51c13c52,I3358c51e into integration

* changes:
build: always prefix section names with `.`
build: communicate correct page size to linker

build: always prefix section names with `.`

Some of our specialized sections are not prefixed with the conventional
period. The compiler uses input section names to derive certain other
section name

build: always prefix section names with `.`

Some of our specialized sections are not prefixed with the conventional
period. The compiler uses input section names to derive certain other
section names (e.g. `.rela.text`, `.relacpu_ops`), and these can be
difficult to select in linker scripts when there is a lack of a
delimiter.

This change introduces the period prefix to all specialized section
names.

BREAKING-CHANGE: All input and output linker section names have been
prefixed with the period character, e.g. `cpu_ops` -> `.cpu_ops`.

Change-Id: I51c13c5266d5975fbd944ef4961328e72f82fc1c
Signed-off-by: Chris Kay <chris.kay@arm.com>

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Merge changes I9c9ed516,I2788eaf6 into integration

* changes:
qemu/qemu_sbsa: fix memory type of secure NOR flash
qemu/qemu_sbsa: spm_mm supports 512 cores

qemu/qemu_sbsa: fix memory type of secure NOR flash

This commit fixes the wrong memory type, secure NOR flash
shall be mapped as MT_DEVICE.

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.or

qemu/qemu_sbsa: fix memory type of secure NOR flash

This commit fixes the wrong memory type, secure NOR flash
shall be mapped as MT_DEVICE.

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Change-Id: I9c9ed51675d84ded675bb56b2e4ec7a08184c602

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qemu/qemu_sbsa: spm_mm supports 512 cores

sbsa-ref in QEMU may create up to 512 cores.
This commit prepares the MP information to support 512 cores.
The number of xlat tables for spm_mm is also incr

qemu/qemu_sbsa: spm_mm supports 512 cores

sbsa-ref in QEMU may create up to 512 cores.
This commit prepares the MP information to support 512 cores.
The number of xlat tables for spm_mm is also increased.

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Change-Id: I2788eaf6d14e188e9b5d1102d359b2899e02df7c

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Merge changes from topic "qemu-sbsa-topology-psci" into integration

* changes:
qemu/qemu_sbsa: add support for sbsa-ref Embedded Controller
qemu/qemu_sbsa: topology is different from qemu so add

Merge changes from topic "qemu-sbsa-topology-psci" into integration

* changes:
qemu/qemu_sbsa: add support for sbsa-ref Embedded Controller
qemu/qemu_sbsa: topology is different from qemu so add handling
qemu/common : change DEVICE2 definition for MMU
qemu/aarch64/plat_helpers.S : calculate the position shift

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qemu/qemu_sbsa: add support for sbsa-ref Embedded Controller

This allows PSCI in TF-A to signal platform power states to QEMU
via a controller in secure space.

This required a sbsa-ref specific ver

qemu/qemu_sbsa: add support for sbsa-ref Embedded Controller

This allows PSCI in TF-A to signal platform power states to QEMU
via a controller in secure space.

This required a sbsa-ref specific version of PSCI functions for the
platform. Also adjusted the MMU range to also include the new EC.

Add a new MMU region for the embedded controller and increase the
size of xlat tables by one for the new region.

Signed-off-by: Graeme Gregory <graeme@nuviainc.com>
Change-Id: Iece8a88947f11e82ab8988e460a8a66ad175a5ee

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