| #
af74739f |
| 14-Mar-2025 |
Mark Dykes <mark.dykes@arm.com> |
Merge "fix(intel): this patch is used to solve DDR and VAB" into integration
|
| #
458b40df |
| 05-Mar-2025 |
Jit Loon Lim <jit.loon.lim@altera.com> |
fix(intel): this patch is used to solve DDR and VAB
The patch provide solutions for:
1. Enable BL31 console logs during run-time.
2. Update VAB initialization.
3. Update DDR size accordin to Linux D
fix(intel): this patch is used to solve DDR and VAB
The patch provide solutions for:
1. Enable BL31 console logs during run-time.
2. Update VAB initialization.
3. Update DDR size accordin to Linux DTS configuration.
4. Solve VAB CCERT address issue.
Change-Id: I41eb0fab747de5010d369e845c33a45decb41e21
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>
show more ...
|
| #
8de2ae5f |
| 16-Oct-2024 |
Mark Dykes <mark.dykes@arm.com> |
Merge "fix(intel): update outdated code for Linux direct boot" into integration
|
| #
21a01dac |
| 04-Oct-2024 |
Sieu Mun Tang <sieu.mun.tang@intel.com> |
fix(intel): update outdated code for Linux direct boot
1. Update emif rsthdshk macro
2. Update mailbox return status
3. Update bridge return status
Change-Id: I33905508aceb258ac8759c10079b2af977df
fix(intel): update outdated code for Linux direct boot
1. Update emif rsthdshk macro
2. Update mailbox return status
3. Update bridge return status
Change-Id: I33905508aceb258ac8759c10079b2af977df0e0a
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
show more ...
|
| #
44c5f8e5 |
| 22-Aug-2024 |
Mark Dykes <mark.dykes@arm.com> |
Merge changes I23bdbbe1,Ic22ab741 into integration
* changes:
feat(intel): enable VAB support for Intel products
feat(intel): add in SHA384 authentication
|
| #
3eb5640a |
| 19-Jul-2024 |
Sieu Mun Tang <sieu.mun.tang@intel.com> |
feat(intel): enable VAB support for Intel products
This patch is to implement Vendor Authorize Bootloader
support for Intel Agilex, Agilex5 and N5X.
Change-Id: I23bdbbe15b3732775cea028665e2efcbd04b
feat(intel): enable VAB support for Intel products
This patch is to implement Vendor Authorize Bootloader
support for Intel Agilex, Agilex5 and N5X.
Change-Id: I23bdbbe15b3732775cea028665e2efcbd04b3aff
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
show more ...
|
| #
b3a7396d |
| 19-Jan-2024 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge changes Iaa189c54,I8856b495 into integration
* changes:
feat(intel): enable query of fip offset on RSU
feat(intel): support query of fip offset using RSU
|
| #
6cbe2c5d |
| 22-Aug-2023 |
Mahesh Rao <mahesh.rao@intel.com> |
feat(intel): enable query of fip offset on RSU
Enable query of fip offset from QSPI on RSU boot for
Intel agilex and intel agilex5 platform
Change-Id: Iaa189c54723a8656b9691da5849fd86b9986cfa1
Sign
feat(intel): enable query of fip offset on RSU
Enable query of fip offset from QSPI on RSU boot for
Intel agilex and intel agilex5 platform
Change-Id: Iaa189c54723a8656b9691da5849fd86b9986cfa1
Signed-off-by: Mahesh Rao <mahesh.rao@intel.com>
show more ...
|
| #
868f9768 |
| 12-May-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes Ie9451e35,I1815deeb,If277b2b3,Ie2ceaf24,I7996d505, ... into integration
* changes:
fix(intel): add flash dcache after return response for INTEL_SIP_SMC_MBOX_SEND_CMD
fix(intel): ex
Merge changes Ie9451e35,I1815deeb,If277b2b3,Ie2ceaf24,I7996d505, ... into integration
* changes:
fix(intel): add flash dcache after return response for INTEL_SIP_SMC_MBOX_SEND_CMD
fix(intel): extending to support large file size for SHA2/HMAC get digest and verifying
fix(intel): extending to support large file size for SHA-2 ECDSA data signing and signature verifying
fix(intel): extending to support large file size for AES encryption and decryption
feat(intel): support version 2 SiP SVC SMC function ID for mailbox commands
feat(intel): support version 2 SiP SVC SMC function ID for non-mailbox commands
fix(intel): update certificate mask for FPGA Attestation
feat(intel): update to support maximum response data size
feat(intel): support ECDSA HASH Verification
feat(intel): support ECDSA HASH Signing
feat(intel): support ECDH request
feat(intel): support ECDSA SHA-2 Data Signature Verification
feat(intel): support ECDSA SHA-2 Data Signing
feat(intel): support ECDSA Get Public Key
feat(intel): support session based SDOS encrypt and decrypt
feat(intel): support AES Crypt Service
feat(intel): support HMAC SHA-2 MAC verify request
feat(intel): support SHA-2 hash digest generation on a blob
feat(intel): support extended random number generation
feat(intel): support crypto service key operation
feat(intel): support crypto service session
feat(intel): extend attestation service to Agilex family
fix(intel): flush dcache before sending certificate to mailbox
fix(intel): introduce a generic response error code
fix(intel): allow non-secure access to FPGA Crypto Services (FCS)
feat(intel): single certificate feature enablement
feat(intel): initial commit for attestation service
fix(intel): update encryption and decryption command logic
show more ...
|
| #
ad47f142 |
| 11-May-2022 |
Sieu Mun Tang <sieu.mun.tang@intel.com> |
feat(intel): support version 2 SiP SVC SMC function ID for non-mailbox commands
A separated SMC function ID of non-mailbox command
is introduced for the new format of SMC protocol.
The new format o
feat(intel): support version 2 SiP SVC SMC function ID for non-mailbox commands
A separated SMC function ID of non-mailbox command
is introduced for the new format of SMC protocol.
The new format of SMC procotol will be started
using by Zephyr.
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I01cff2739364b1bda2ebb9507ddbcef6095f5d29
show more ...
|
| #
f0f631fd |
| 10-May-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "feat(intel): add support for F2S and S2F bridge SMC with mask to enable, disable and reset bridge" into integration
|
| #
11f4f030 |
| 05-May-2022 |
Sieu Mun Tang <sieu.mun.tang@intel.com> |
feat(intel): add support for F2S and S2F bridge SMC with mask to enable, disable and reset bridge
This adds F2S and S2F bridge enable, disable and reset
sequence to enable, disable and reset properl
feat(intel): add support for F2S and S2F bridge SMC with mask to enable, disable and reset bridge
This adds F2S and S2F bridge enable, disable and reset
sequence to enable, disable and reset properly the bridges
in SMC call or during reset.
The reset is also maskable as the SMC from uboot can
pass in the bridge mask when requesting for bridge
enable or disable.
Signed-off-by: Loh Tien Hock <tien.hock.loh@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Ie144518c591664ef880016c9b3706968411bbf21
show more ...
|
| #
394f2ea0 |
| 25-Apr-2022 |
Lauren Wehrmeister <lauren.wehrmeister@arm.com> |
Merge changes Iccfa7ec6,Ide9a7af4 into integration
* changes:
feat(intel): add macro to switch between different UART PORT
feat(intel): add SMC support for ROM Patch SHA384 mailbox
|
| #
447e699f |
| 05-Aug-2021 |
Boon Khai Ng <boon.khai.ng@intel.com> |
feat(intel): add macro to switch between different UART PORT
HSD #1509626040:
This patch is to add the flexibility for BL2 and BL31
to choose different UART output port at platform_def.h
using param
feat(intel): add macro to switch between different UART PORT
HSD #1509626040:
This patch is to add the flexibility for BL2 and BL31
to choose different UART output port at platform_def.h
using parameter PLAT_INTEL_UART_BASE
This patch also fixing the plat_helpers.S where the
UART BASE is hardcoded to PLAT_UART0_BASE. It is then
switched to CRASH_CONSOLE_BASE.
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Change-Id: Iccfa7ec64e4955b531905778be4da803045d3c8f
show more ...
|
| #
a78c6c96 |
| 28-Feb-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "fix(intel): assert if bl_mem_params is NULL pointer" into integration
|
| #
b5d2b4d5 |
| 28-Feb-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "fix(intel): enable HPS QSPI access by default" into integration
|
| #
35fe7f40 |
| 12-Jun-2021 |
Siew Chin Lim <elly.siew.chin.lim@intel.com> |
fix(intel): assert if bl_mem_params is NULL pointer
This patch fixes the code issue detected by Klocwork scan. Pointer
'bl_mem_params' returned from call to function 'get_bl_mem_params_node'
may be
fix(intel): assert if bl_mem_params is NULL pointer
This patch fixes the code issue detected by Klocwork scan. Pointer
'bl_mem_params' returned from call to function 'get_bl_mem_params_node'
may be NULL and the NULL pointer may be caused the system crash. Update
the code to assert if unexpected NULL pointer is returned.
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Change-Id: I00f3132a6104618cadce26aa303c0b46b5921d5b
show more ...
|
| #
000267be |
| 06-Oct-2020 |
Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> |
fix(intel): enable HPS QSPI access by default
Request ownership and direct access to QSPI by default in BL2.
Previously, this is only done on QSPI boot mode.
Signed-off-by: Abdul Halim, Muhammad Ha
fix(intel): enable HPS QSPI access by default
Request ownership and direct access to QSPI by default in BL2.
Previously, this is only done on QSPI boot mode.
Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ie222bbf9d719f2f70f89d4739c285efe6df4c955
show more ...
|
| #
160bfb27 |
| 08-Apr-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "mmc_device_info" into integration
* changes:
plat/st: do not keep mmc_device_info in stack
plat/intel: do not keep mmc_device_info in stack
plat/hisilicon: do not kee
Merge changes from topic "mmc_device_info" into integration
* changes:
plat/st: do not keep mmc_device_info in stack
plat/intel: do not keep mmc_device_info in stack
plat/hisilicon: do not keep mmc_device_info in stack
show more ...
|
| #
5cb7fc82 |
| 22-Mar-2021 |
Yann Gautier <yann.gautier@foss.st.com> |
plat/intel: do not keep mmc_device_info in stack
Create a dedicated static struct mmc_device_info mmc_info mmc_info
instead of having this in stack.
A boot issue has been seen on some platform when
plat/intel: do not keep mmc_device_info in stack
Create a dedicated static struct mmc_device_info mmc_info mmc_info
instead of having this in stack.
A boot issue has been seen on some platform when applying patch [1].
[1] 13f3c5166f1 ("mmc:prevent accessing to the released space in case of wrong usage")
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: Id52c0be61a30f453a551385883eaf3cbe32b04b9
show more ...
|
| #
141568da |
| 08-Jun-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "fix-agilex-initialization" into integration
* changes:
plat: intel: Additional instruction required to enable global timer
plat: intel: Fix CCU initialization for Agile
Merge changes from topic "fix-agilex-initialization" into integration
* changes:
plat: intel: Additional instruction required to enable global timer
plat: intel: Fix CCU initialization for Agilex
plat: intel: Add FPGAINTF configuration to when configuring pinmux
plat: intel: set DRVSEL and SMPLSEL for DWMMC
plat: intel: Fix clock configuration bugs
show more ...
|
| #
aea772dd |
| 11-May-2020 |
Tien Hock Loh <tien.hock.loh@intel.com> |
plat: intel: set DRVSEL and SMPLSEL for DWMMC
DRVSEL and SMPLSEL needs to be set so that it can properly go into full
speed mode. This needs to be done in EL3 as the registers are secured.
Signed-o
plat: intel: set DRVSEL and SMPLSEL for DWMMC
DRVSEL and SMPLSEL needs to be set so that it can properly go into full
speed mode. This needs to be done in EL3 as the registers are secured.
Signed-off-by: Tien Hock Loh <tien.hock.loh@intel.com>
Change-Id: Ia2f348e7742ff7b76da74d392ef1ce71e2f41677
show more ...
|
| #
351d358f |
| 28-Feb-2020 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "intel: Enable EMAC PHY in Intel FPGA platform" into integration
|
| #
896d684d |
| 25-Feb-2020 |
Mark Dykes <mardyk01@review.trustedfirmware.org> |
Merge changes from topic "console_t_cleanup" into integration
* changes:
marvell: Consolidate console register calls
uniphier: Use generic console_t data structure
spe: Use generic console_t d
Merge changes from topic "console_t_cleanup" into integration
* changes:
marvell: Consolidate console register calls
uniphier: Use generic console_t data structure
spe: Use generic console_t data structure
LS 16550: Use generic console_t data structure
stm32: Use generic console_t data structure
rcar: Use generic console_t data structure
a3700: Use generic console_t data structure
16550: Use generic console_t data structure
imx: Use generic console_t data structure
show more ...
|
| #
98964f05 |
| 25-Jan-2020 |
Andre Przywara <andre.przywara@arm.com> |
16550: Use generic console_t data structure
Since now the generic console_t structure holds the UART base address as
well, let's use that generic location and drop the UART driver specific
data stru
16550: Use generic console_t data structure
Since now the generic console_t structure holds the UART base address as
well, let's use that generic location and drop the UART driver specific
data structure at all.
Change-Id: I5c2fe3b6a667acf80c808cfec4a64059a2c9c25f
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
show more ...
|