| #
e86efe4b |
| 31-Mar-2025 |
Yann Gautier <yann.gautier@st.com> |
Merge changes I1dfb95aa,I9eb61c48 into integration
* changes:
feat(intel): support FCS commands with SiPSVC V3 framework
feat(intel): implementation of SiPSVC-V3 protocol framework
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| #
204d5e67 |
| 05-Mar-2025 |
Sieu Mun Tang <sieu.mun.tang@altera.com> |
feat(intel): implementation of SiPSVC-V3 protocol framework
- Develop SiPSVC-V3 framework to support async/yielding SMC calls.
- Add support for multi clients with multiple jobs running together.
-
feat(intel): implementation of SiPSVC-V3 protocol framework
- Develop SiPSVC-V3 framework to support async/yielding SMC calls.
- Add support for multi clients with multiple jobs running together.
- Add support for SDM doorbell interrupt handling.
- Keep the framework backward compatible with V1 clients.
- Enable the framework on all the platform Agilex7, Agilex5, N5X,
and Stratix10.
Change-Id: I9eb61c48be89867b4227e084493bfcf67cbe7924
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@altera.com>
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| #
92f8e898 |
| 19-Dec-2023 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "fix(intel): bl31 overwrite OCRAM configuration" into integration
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| #
cfbac595 |
| 19-Oct-2023 |
Jit Loon Lim <jit.loon.lim@intel.com> |
fix(intel): bl31 overwrite OCRAM configuration
U-boot is allowed to configure OCRAM access. However
ATF BL31 will overwrite it. Thus removing this function
to allow for proper configuration.
Change
fix(intel): bl31 overwrite OCRAM configuration
U-boot is allowed to configure OCRAM access. However
ATF BL31 will overwrite it. Thus removing this function
to allow for proper configuration.
Change-Id: I45173ef8f472c3620486de0cbf6452ba5f78be01
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
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| #
4bd8c929 |
| 09-May-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes I1bfa797e,I0ec7a70e into integration
* changes:
fix(tree): correct some typos
fix(rockchip): use semicolon instead of comma
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| #
1b491eea |
| 13-Feb-2023 |
Elyes Haouas <ehaouas@noos.fr> |
fix(tree): correct some typos
found using codespell (https://github.com/codespell-project/codespell).
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I1bfa797e3460adddeefa916bb68e22beddaf6
fix(tree): correct some typos
found using codespell (https://github.com/codespell-project/codespell).
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I1bfa797e3460adddeefa916bb68e22beddaf6373
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| #
394f2ea0 |
| 25-Apr-2022 |
Lauren Wehrmeister <lauren.wehrmeister@arm.com> |
Merge changes Iccfa7ec6,Ide9a7af4 into integration
* changes:
feat(intel): add macro to switch between different UART PORT
feat(intel): add SMC support for ROM Patch SHA384 mailbox
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| #
447e699f |
| 05-Aug-2021 |
Boon Khai Ng <boon.khai.ng@intel.com> |
feat(intel): add macro to switch between different UART PORT
HSD #1509626040:
This patch is to add the flexibility for BL2 and BL31
to choose different UART output port at platform_def.h
using param
feat(intel): add macro to switch between different UART PORT
HSD #1509626040:
This patch is to add the flexibility for BL2 and BL31
to choose different UART output port at platform_def.h
using parameter PLAT_INTEL_UART_BASE
This patch also fixing the plat_helpers.S where the
UART BASE is hardcoded to PLAT_UART0_BASE. It is then
switched to CRASH_CONSOLE_BASE.
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Change-Id: Iccfa7ec64e4955b531905778be4da803045d3c8f
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| #
5e29432e |
| 09-Mar-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes I713f6e93,Iac4fbf4d,I43d02c77,Iadecd544,Ib31f9c4a, ... into integration
* changes:
build(intel): enable access to on-chip ram in BL31 for N5X
fix(intel): make FPGA memory configura
Merge changes I713f6e93,Iac4fbf4d,I43d02c77,Iadecd544,Ib31f9c4a, ... into integration
* changes:
build(intel): enable access to on-chip ram in BL31 for N5X
fix(intel): make FPGA memory configurations platform specific
fix(intel): fix ECC Double Bit Error handling
build(intel): define a macro for SIMICS build
build(intel): add N5X as a new Intel platform
build(intel): initial commit for crypto driver
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| #
39f262cf |
| 21-May-2021 |
Boon Khai Ng <boon.khai.ng@intel.com> |
build(intel): enable access to on-chip ram in BL31 for N5X
This adds the ncore ccu access and enable access to the
on-chip ram for N5X device in BL31.
Signed-off-by: Boon Khai Ng <boon.khai.ng@inte
build(intel): enable access to on-chip ram in BL31 for N5X
This adds the ncore ccu access and enable access to the
on-chip ram for N5X device in BL31.
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I713f6e93d33b6e91705547477ca32cfba5c8c13d
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| #
325eb35d |
| 07-Mar-2022 |
Sieu Mun Tang <sieu.mun.tang@intel.com> |
build(intel): add N5X as a new Intel platform
This commit adds a new Intel platform called N5X.
This preliminary patch only have Bl31 support.
Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muh
build(intel): add N5X as a new Intel platform
This commit adds a new Intel platform called N5X.
This preliminary patch only have Bl31 support.
Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Ib31f9c4a5a0dabdce81c1d5b0d4776188add7195
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