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1c408d3c |
| 01-Mar-2024 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "imx8ulp_support" into integration
* changes: docs(maintainers): add the maintainers for imx8ulp docs(imx8ulp): add imx8ulp platform fix(imx8ulp): increase the mmap re
Merge changes from topic "imx8ulp_support" into integration
* changes: docs(maintainers): add the maintainers for imx8ulp docs(imx8ulp): add imx8ulp platform fix(imx8ulp): increase the mmap region num feat(imx8ulp): adjust the dram mapped region feat(imx8ulp): ddrc switch auto low power and software interface feat(imx8ulp): add some delay before cmc1 access feat(imx8ulp): add a flag check for the ddr status fix(imx8ulp): add sw workaround for csi/hotplug test hang feat(imx8ulp): adjust the voltage when sys dvfs enabled feat(imx8ulp): enable the DDR frequency scaling support fix(imx8ulp): fix suspend/resume issue when DBD owner is s400 only feat(imx8ulp): update XRDC for ELE to access DDR with CA35 DID feat(imx8ulp): add memory region policy feat(imx8ulp): protect TEE region for secure access only feat(imx8ulp): add trusty support feat(imx8ulp): add OPTEE support feat(imx8ulp): update the upower config for power optimization feat(imx8ulp): allow RTD to reset APD through MU feat(imx8ulp): not power off LPAV PD when LPAV owner is RTD feat(imx8ulp): add system power off support feat(imx8ulp): add APD power down mode(PD) support in system suspend feat(imx8ulp): add the basic support for idle & system suspned feat(imx8ulp): enable 512KB cache after resume on imx8ulp feat(imx8ulp): add the initial XRDC support feat(imx8ulp): allocated caam did for the non secure world feat(imx8ulp): add i.MX8ULP basic support build(changelog): add new scopes for nxp imx8ulp platform feat(scmi): add scmi sensor support
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047d7d1b |
| 02-Aug-2023 |
Jacky Bai <ping.bai@nxp.com> |
fix(imx8ulp): increase the mmap region num
the mmap region num is not enough for the mmap regions, so increase it, increase the xlat_table num too.
Signed-off-by: Jacky Bai <ping.bai@nxp.com> Chang
fix(imx8ulp): increase the mmap region num
the mmap region num is not enough for the mmap regions, so increase it, increase the xlat_table num too.
Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: I2a2515b291e96cc12398a2c2c526351342811fff
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8d50c91b |
| 27-Jul-2023 |
Ji Luo <ji.luo@nxp.com> |
feat(imx8ulp): adjust the dram mapped region
below commit mapped 16 MB memory from the start of DRAM(0x80000000), which may have conflict with the shared memory used by Trusty OS: LF-8819: plat: i
feat(imx8ulp): adjust the dram mapped region
below commit mapped 16 MB memory from the start of DRAM(0x80000000), which may have conflict with the shared memory used by Trusty OS: LF-8819: plat: imx8ulp: ddrc switch auto low power and software interface
change the mapped memory to 'vdev0buffer' reserved memory (0x8ff00000) to avoid memory conflict. This commit also bumps the XTLB tables to avoid mapping failure.
Signed-off-by: Ji Luo <ji.luo@nxp.com> Change-Id: I1a7af958af47e3fc9955d0a80d1649971e843eab
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ee25e6a5 |
| 14-Apr-2023 |
Adrian Alonso <adrian.alonso@nxp.com> |
feat(imx8ulp): ddrc switch auto low power and software interface
Enable switch between DDRC Auto low power and software/hardware control modes DDRC Auto low-power mode is used when system is active,
feat(imx8ulp): ddrc switch auto low power and software interface
Enable switch between DDRC Auto low power and software/hardware control modes DDRC Auto low-power mode is used when system is active, software/hardware control mode is used when going into suspend. Enable switching between Auto mode and SW/HW mode in enter/exit retention routines.
Set LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2 Max setting to allow LPDDR_EN_CLKGATE reload LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2 to exit retention mode
Signed-off-by: Pascal Mareau <pascal.mareau@nxp.com> Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com> Signed-off-by: Hongting Ting <hongting.dong@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: I3c4b6f7bc6ca02649ff27cd3d9a0c50dab3a3ad0
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e8530419 |
| 18-Jun-2021 |
Ji Luo <ji.luo@nxp.com> |
feat(imx8ulp): add trusty support
Support trusty on imx8ulp.
Signed-off-by: Ji Luo <ji.luo@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: I7ada2557023e271a721d50bfe7fd20b5f01cb128
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e7b82a7d |
| 14-Jun-2021 |
Clement Faure <clement.faure@nxp.com> |
feat(imx8ulp): add OPTEE support
Add opteed support for imx8ulp.
Signed-off-by: Clement Faure <clement.faure@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: Iddf6f164b7146332e99de42
feat(imx8ulp): add OPTEE support
Add opteed support for imx8ulp.
Signed-off-by: Clement Faure <clement.faure@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: Iddf6f164b7146332e99de42fcbbf9c892eb1d994
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ea1f7a2e |
| 21-Nov-2022 |
Ye Li <ye.li@nxp.com> |
feat(imx8ulp): allow RTD to reset APD through MU
Clear HRM bit in MU0_B CCR0 register to allow RTD to reset APD. The action needs at both ATF init and APD resume.
Signed-off-by: Ye Li <ye.li@nxp.co
feat(imx8ulp): allow RTD to reset APD through MU
Clear HRM bit in MU0_B CCR0 register to allow RTD to reset APD. The action needs at both ATF init and APD resume.
Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: I2475e34b13f57818580a478ab567bfb9fc6cf174
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478af8d3 |
| 25-Jun-2021 |
Jacky Bai <ping.bai@nxp.com> |
feat(imx8ulp): add APD power down mode(PD) support in system suspend
The APD can be put into PD mode when linux suspend(mem). This patch add the support for it. As the whole AP domain's context will
feat(imx8ulp): add APD power down mode(PD) support in system suspend
The APD can be put into PD mode when linux suspend(mem). This patch add the support for it. As the whole AP domain's context will be lost, so we must save the necessary HW module states before entering PD mode, and we need to restore those contexts when system wake up. Fot details about which HW module's state will be lost, please refer to the RM.
When APD enter PD mode, only the wakeup event connected to the WUU can wakeup APD successfully. The upower wakeup source is used to wakeup APD by RTD due to the factor that the MU between A core & M core is not connected into WUU to generate wakeup event.
as the SRAM0 will be power down when APD enters PD mode, so we need to re-init the scmi channels(resides in the SRAM0). otherwise the SCMI can NOT work anymore.
Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Change-Id: I44b0cdc8397e5d6a82081ea6746542e9fa4b9fc1
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daa4478a |
| 18-Sep-2023 |
Jacky Bai <ping.bai@nxp.com> |
feat(imx8ulp): add the basic support for idle & system suspned
Add basic support for the cpuidle(cluster retention) and system suspend support using the HW sleep mode.
When system enter low power m
feat(imx8ulp): add the basic support for idle & system suspned
Add basic support for the cpuidle(cluster retention) and system suspend support using the HW sleep mode.
When system enter low power mode after doing reboot twice, APD will be failed to exit from low power mode successfully. it is because that after secondary reboot, upower will modify the default power switch config, then DDR will be off wrongly. So config the low power mode info explicitly before APD entering any low power mode.
Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: Ib68bfdfd4b925541e343aef4a5296a542451f86b
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7c5eedca |
| 04-Aug-2021 |
Pankaj Gupta <pankaj.gupta@nxp.com> |
feat(imx8ulp): allocated caam did for the non secure world
JR1, JR2 and JR3 are available for use by the non secure world. Setup the A35 core DID for these job rings.
Signed-off-by: Varun Sethi <v.
feat(imx8ulp): allocated caam did for the non secure world
JR1, JR2 and JR3 are available for use by the non secure world. Setup the A35 core DID for these job rings.
Signed-off-by: Varun Sethi <v.sethi@nxp.com> Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: If64d4ce11ebff49a2405d8b561b344fcd7b2614f
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fcd41e86 |
| 02-Jul-2020 |
Jacky Bai <ping.bai@nxp.com> |
feat(imx8ulp): add i.MX8ULP basic support
Add the basic support for i.MX8ULP.
The i.MX 8ULP family of processors features NXP’s advanced implementation of the dual Arm Cortex-A35 cores alongside an
feat(imx8ulp): add i.MX8ULP basic support
Add the basic support for i.MX8ULP.
The i.MX 8ULP family of processors features NXP’s advanced implementation of the dual Arm Cortex-A35 cores alongside an Arm Cortex-M33. This combined architecture enables the device to run a rich operating system (such as Linux) on the Cortex-A35 core and an RTOS (such as FreeRTOS) on the Cortex-M33 core. It also includes a Cadence Tensilica Fusion DSP for low-power audio and a HiFi4 DSP for advanced audio and machine learning applications.
Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: I12df622b95960bcdf7da52e4c66470a700690e36
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