Merge changes from topic "xlnx_enhancement_on_secure_and_non_secure_flag" into integration

* changes:
feat(xilinx): use common SECURE/NON_SECURE macro
fix(xilinx): incorrect usage of SECURE_FLAG

Merge changes from topic "xlnx_enhancement_on_secure_and_non_secure_flag" into integration

* changes:
feat(xilinx): use common SECURE/NON_SECURE macro
fix(xilinx): incorrect usage of SECURE_FLAG for psci

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feat(xilinx): use common SECURE/NON_SECURE macro

Remove platform-specific macro definitions such as SECURE_FLAG and
NON_SECURE_FLAG, and replace them with the common macros SECURE and
NON_SECURE acr

feat(xilinx): use common SECURE/NON_SECURE macro

Remove platform-specific macro definitions such as SECURE_FLAG and
NON_SECURE_FLAG, and replace them with the common macros SECURE and
NON_SECURE across all AMD-Xilinx platforms.

Change-Id: I95465e29ac8a9370da135c2113203c3206ecfec0
Signed-off-by: Ronak Jain <ronak.jain@amd.com>

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Merge "fix(versal-net): add fallback on handoff failure" into integration

fix(versal-net): add fallback on handoff failure

On the Versal-Net platform, booting can fail during ELF loading due to
the absence of a PLM handoff, preventing the system from booting
further.

To

fix(versal-net): add fallback on handoff failure

On the Versal-Net platform, booting can fail during ELF loading due to
the absence of a PLM handoff, preventing the system from booting
further.

To address this, a fallback mechanism has been introduced that allows
the boot process to continue even if the PLM handoff is not provided
only in debug builds with jtag boot mode.

Change-Id: Ib8d92ab8400b7a63b05ae8c77b40b30fe7abaab8
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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Merge changes from topic "xlnx_fix_plat_single_ret" into integration

* changes:
fix(versal2): modify function to have single return
fix(versal-net): modify function to have single return
fix(v

Merge changes from topic "xlnx_fix_plat_single_ret" into integration

* changes:
fix(versal2): modify function to have single return
fix(versal-net): modify function to have single return
fix(versal): modify function to have single return
fix(xilinx): modify function to have single return
fix(zynqmp): modify function to have single return
fix(versal-net): add unsigned suffix to match data type
fix(versal): add unsigned suffix to match data type
fix(versal2): add missing curly braces
fix(versal-net): add missing curly braces
fix(zynqmp): add missing curly braces

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fix(versal-net): modify function to have single return

This corrects the MISRA violation C2012-15.5:
A function should have a single point of exit at the end.
Introduced a temporary variable to stor

fix(versal-net): modify function to have single return

This corrects the MISRA violation C2012-15.5:
A function should have a single point of exit at the end.
Introduced a temporary variable to store the return value to
ensure single return for the function.

Change-Id: Ib8b3339f32031a3657f6c349763a20a99fd828e7
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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Merge changes from topic "xlnx_fix_plat_extn_decl_link" into integration

* changes:
fix(versal2): variable conflicting with external linkage
fix(versal-net): variable conflicting with external l

Merge changes from topic "xlnx_fix_plat_extn_decl_link" into integration

* changes:
fix(versal2): variable conflicting with external linkage
fix(versal-net): variable conflicting with external linkage
fix(versal): variable conflicting with external linkage
fix(zynqmp): variable conflicting with external linkage
fix(versal2): add external declaration
fix(versal): add external declaration
fix(zynqmp): add external declaration

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fix(versal-net): variable conflicting with external linkage

This corrects the MISRA violation C2012-5.8:
Identifiers that define objects or functions with
external linkage shall be unique.
Modify th

fix(versal-net): variable conflicting with external linkage

This corrects the MISRA violation C2012-5.8:
Identifiers that define objects or functions with
external linkage shall be unique.
Modify the variable name to prevent conflict with
external object linkage.

Change-Id: Icba1860d789d3826a58b3d83b65ca86a7b364c46
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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Merge changes from topic "xlnx_set_freq" into integration

* changes:
refactor(xilinx): move plat_get_syscnt_freq2 to common file
refactor(versal-net): rename VERSAL_NET_IOU_SCNTRS register to ge

Merge changes from topic "xlnx_set_freq" into integration

* changes:
refactor(xilinx): move plat_get_syscnt_freq2 to common file
refactor(versal-net): rename VERSAL_NET_IOU_SCNTRS register to generic
fix(versal-net): setup counter frequency
fix(versal): initialize cntfrq_el0 register

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refactor(xilinx): move plat_get_syscnt_freq2 to common file

The code in the AMD-Xilinx platform for Versal and Versal NET is being
refactored to move the plat_get_syscnt_freq2() function to a common

refactor(xilinx): move plat_get_syscnt_freq2 to common file

The code in the AMD-Xilinx platform for Versal and Versal NET is being
refactored to move the plat_get_syscnt_freq2() function to a common
file. This common function is utilized for obtaining the CPU clock
frequency from the platform.

Change-Id: I7a4c3fa43a2941d51cacd259c57b24e545aea848
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>

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refactor(versal-net): rename VERSAL_NET_IOU_SCNTRS register to generic

Refactor, the macro named VERSAL_NET_IOU_SCNTRS is being renamed to a more
generic macro name, which will be used in common cod

refactor(versal-net): rename VERSAL_NET_IOU_SCNTRS register to generic

Refactor, the macro named VERSAL_NET_IOU_SCNTRS is being renamed to a more
generic macro name, which will be used in common code to enable reuse
across various platforms.

Change-Id: I548437e0fe2d73b196468bc92029f8099ea1f8d1
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>

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fix(versal-net): setup counter frequency

Refactor the system counter configuration into the
syscnt_freq_config_setup() function as it involves timestamp and
system counter configuration, which requi

fix(versal-net): setup counter frequency

Refactor the system counter configuration into the
syscnt_freq_config_setup() function as it involves timestamp and
system counter configuration, which requires early configuration for
clock setup and read the value of the IOU_SCNTRS_BASE_FREQ register
using mmio_read_32() to determine the counter frequency.

If the counter frequency is zero, the system will set the default CPU
clocks constants in TF-A and displays message. However, if the counter
frequency is non-zero, the program will return the value stored in the
IOU_SCNTRS_BASE_FREQ register.

The issue lies in dcc_status_timeout(),function verifying timeout
status, particularly within timeout_cnt_us2cnt(), converting
microseconds to counter ticks using read_cntfrq_el0(), which returns
zero. timeout_elapsed() then checks if the current counter from
read_cntpct_el0() exceeds the expiration count, reached to timeout.

After the function set_cnt_freq() writes into the counter frequency
register, the function timeout_cnt_us2cnt() is used to obtain the
appropriate counter ticks. Subsequently, the function timeout_elapsed()
checks whether the current counter value read_cntpct_el0() has
exceeded the specified expiration count. If it has, this indicates
that the timeout has lapsed.

Change-Id: Ib9ed3493d22f23c832f8bb7d11c4f727fe1ebe3c
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>

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Merge changes from topic "xlnx_tsp_feat" into integration

* changes:
docs(versal-net): add TSP build documentation
docs(versal): add TSP build documentation
feat(versal-net): add tsp support

Merge changes from topic "xlnx_tsp_feat" into integration

* changes:
docs(versal-net): add TSP build documentation
docs(versal): add TSP build documentation
feat(versal-net): add tsp support
feat(versal): add tsp support
refactor(xilinx): add generic TSP makefile
chore(zynqmp): reorganize tsp code into common path
refactor(xilinx): rename platform function to generic name

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refactor(xilinx): rename platform function to generic name

Refactor two platform specific functions, plat_versal_get_mmap() and
plat_versal_net_get_mmap(), to use a more generic function name
plat_g

refactor(xilinx): rename platform function to generic name

Refactor two platform specific functions, plat_versal_get_mmap() and
plat_versal_net_get_mmap(), to use a more generic function name
plat_get_mmap(). The function can be used in the common code to
obtain memory region.

Change-Id: I3eeb24aff217eef30af60a7742cbebe9d3b2edce
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>

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Merge changes from topic "xlnx_dtb_console" into integration

* changes:
feat(versal-net): retrieval of console information from dtb
feat(versal): retrieval of console information from dtb
refa

Merge changes from topic "xlnx_dtb_console" into integration

* changes:
feat(versal-net): retrieval of console information from dtb
feat(versal): retrieval of console information from dtb
refactor(xilinx): create generic function for clock retrieval
feat(zynqmp): retrieval of console information from dtb

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refactor(xilinx): create generic function for clock retrieval

Refactors the code in the AMD-Xilinx platform for Versal and Versal NET
to create a more generic function for obtaining clock signals
fr

refactor(xilinx): create generic function for clock retrieval

Refactors the code in the AMD-Xilinx platform for Versal and Versal NET
to create a more generic function for obtaining clock signals
from the platform. The new function get_uart_clk is specific to each
platform and providing greater flexibility for clock signal retrieval
in various parts of the codebase.

Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: Iff67315339b2651c9bea73af0d89fcbad2bb332a

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Merge changes from topic "xlnx_smcc_soc_id" into integration

* changes:
feat(versal-net): add support for SMCC ARCH SOC ID
feat(versal): add support for SMCC ARCH SOC ID
refactor(versal-net):

Merge changes from topic "xlnx_smcc_soc_id" into integration

* changes:
feat(versal-net): add support for SMCC ARCH SOC ID
feat(versal): add support for SMCC ARCH SOC ID
refactor(versal-net): move macros to common header
feat(xilinx): add support to get chipid

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refactor(versal-net): move macros to common header

Move the macros to common header from platform specific folder, so that
the same macros can be re-used in other platforms.

Change-Id: I355b024f5e8

refactor(versal-net): move macros to common header

Move the macros to common header from platform specific folder, so that
the same macros can be re-used in other platforms.

Change-Id: I355b024f5e870c6fc104598bc571dbaa29503ae2
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

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Merge "feat(xilinx): sync copyright format" into integration

feat(xilinx): sync copyright format

Use the same format in all files 's/Copyright (C)/Copyright (c)/g'.

Change-Id: I0e200eb135e7369d0e6b3b694acd406ec10ca9e7
Signed-off-by: Michal Simek <michal.sime

feat(xilinx): sync copyright format

Use the same format in all files 's/Copyright (C)/Copyright (c)/g'.

Change-Id: I0e200eb135e7369d0e6b3b694acd406ec10ca9e7
Signed-off-by: Michal Simek <michal.simek@amd.com>

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Merge "style(xilinx): replace ARM by Arm in copyrights" into integration

style(xilinx): replace ARM by Arm in copyrights

The commit 6bb49c876c75 ("style(hooks): adds Arm copyright style fix")
is enforcing proper case for ARM. That's why fix it in plat/xilinx to
make sure

style(xilinx): replace ARM by Arm in copyrights

The commit 6bb49c876c75 ("style(hooks): adds Arm copyright style fix")
is enforcing proper case for ARM. That's why fix it in plat/xilinx to
make sure that pre-commit.copyright won't be touching platform specific
files.

Change-Id: I49c66e18d46ed871a6aa128c9b2a403d0cf83416
Signed-off-by: Michal Simek <michal.simek@amd.com>

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Merge "feat(versal_net): add support for QEMU COSIM platform" into integration

feat(versal_net): add support for QEMU COSIM platform

QEMU COSIM platform is equivalent to qemu with additional cosim
extensions, so just switching platform_id to QEMU if QEMU_COSIM is
detected.

Si

feat(versal_net): add support for QEMU COSIM platform

QEMU COSIM platform is equivalent to qemu with additional cosim
extensions, so just switching platform_id to QEMU if QEMU_COSIM is
detected.

Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: I922d10b1605c7f900158fa7fbe82571d3b9d4792

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Merge changes from topic "xilinx-versal-net" into integration

* changes:
feat(versal-net): add support for platform management
feat(versal-net): add support for IPI
feat(versal-net): add SMP s

Merge changes from topic "xilinx-versal-net" into integration

* changes:
feat(versal-net): add support for platform management
feat(versal-net): add support for IPI
feat(versal-net): add SMP support for Versal NET
feat(versal-net): add support for Xilinx Versal NET platform
feat(versal-net): add documentation for Versal NET SoC

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