Merge "fix(intel): solve agilex warm reset issue" into integration

fix(intel): solve agilex warm reset issue

Agilex warm reset not able to trigger due to the system not able to
detect the magic number. ATF only able to solve for boot core.
For secondary cores, Linu

fix(intel): solve agilex warm reset issue

Agilex warm reset not able to trigger due to the system not able to
detect the magic number. ATF only able to solve for boot core.
For secondary cores, Linux need to update psci driver to WFI
the cores in EL3. Original Linux WFI is EL1.
Thus causing secondary cores not working

Change-Id: I5470abc19a09e45f16c4cd0049dd20e6534435bb
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

show more ...

Merge "fix(intel): update TFA to patch for Linux 6.12 rebase warning message" into integration

fix(intel): update TFA to patch for Linux 6.12 rebase warning message

On MMU-500 r2p0+ (used in newer SoCFPGA platforms),
we need to clear the SMMU_sACR.CACHE_LOCK bit
so the normal world can write

fix(intel): update TFA to patch for Linux 6.12 rebase warning message

On MMU-500 r2p0+ (used in newer SoCFPGA platforms),
we need to clear the SMMU_sACR.CACHE_LOCK bit
so the normal world can write to SMMU_CBn_ACTLR.

Change-Id: I0d0d227950508a2969fe0fe2eddbe6894efe54bc
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

show more ...

Merge "fix(intel): update warm reset routine and bootscratch register usage" into integration

fix(intel): update warm reset routine and bootscratch register usage

Agilex5 platform:
Boot scratch COLD6 register is meant for Customer use only.
So, use Intel specific COLD3 register with [5:2]bit

fix(intel): update warm reset routine and bootscratch register usage

Agilex5 platform:
Boot scratch COLD6 register is meant for Customer use only.
So, use Intel specific COLD3 register with [5:2]bits to
determine the warm reset and SMP boot requests.
Also handle the unaligned DEVICE/IO memory store and load
in the assembly entrypoint startup code.

Agilex, Stratix10, N5X platforms:
Use only the LSB 4bits [3:0] of the boot scratch COLD6 register
to detect the warm reset request.

Change-Id: I4fd6e63fe0bd42ddcb4a3f81c7a7295bdc8ca65f
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

show more ...

Merge "feat(intel): add build option for boot source" into integration

Merge "fix(intel): refactor SDMMC driver for Altera products" into integration

fix(intel): refactor SDMMC driver for Altera products

Refactor to be more robust. Removed duplicated and not used functions.
Add in ADMA read.

Change-Id: I1a5a00397ece6f9ccc5916225ab5317010b01b52
S

fix(intel): refactor SDMMC driver for Altera products

Refactor to be more robust. Removed duplicated and not used functions.
Add in ADMA read.

Change-Id: I1a5a00397ece6f9ccc5916225ab5317010b01b52
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

show more ...

feat(intel): add build option for boot source

Existing boot source is hardcoded in socfpga_plat_def.h.
To change boot source, user need to update code.
Thus adding this will remove the code update n

feat(intel): add build option for boot source

Existing boot source is hardcoded in socfpga_plat_def.h.
To change boot source, user need to update code.
Thus adding this will remove the code update needed when
need to change boot source.

Also, it will have ARM_LINUX_KERNEL_AS_BL33 flag for each
platform in platform.mk. This will be easily to control
based on platform build.

Change-Id: I383beb8cbca5ec0f247221ad42796554adc3daae
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

show more ...

Merge "fix(intel): update all the platforms hand-off data offset value" into integration

fix(intel): update all the platforms hand-off data offset value

Move the hand-off data offset value from the common
platform header file to each socfpga platform specific
header file.

Change-Id: Ic

fix(intel): update all the platforms hand-off data offset value

Move the hand-off data offset value from the common
platform header file to each socfpga platform specific
header file.

Change-Id: Icfe917f788814c329659c44e298cf05d6e3d0dd9
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

show more ...

Merge "fix(intel): flush L1/L2/L3/Sys cache before HPS cold reset" into integration

Merge "fix(intel): update preloaded_bl33_base for legacy product" into integration

fix(intel): update preloaded_bl33_base for legacy product

Update preloaded_bl33_base for legacy product for Yocto.

The Yocto Jenkins build was initially configured to build products
where the start

fix(intel): update preloaded_bl33_base for legacy product

Update preloaded_bl33_base for legacy product for Yocto.

The Yocto Jenkins build was initially configured to build products
where the starting of the DDR is from 0x0000 0000. And if there is
no NS_image_offset set, the Jenkins is not able to acquire the correct
address offset to boot up the system. However, in the direct OS boot,
there is no issue as the user shall always include the address offset
during the compilation phase. Otherwise, the code shall execute the
default address offset. Besides that, this also provides the
flexibility to user to customize their SoC design by not restricted
to the default address.

SDMMC block size. It was changed due to the need when boot to Linux.
Kernel.itb size is big thus we have to increase the available reading
block size. Otherwise for normal U-boot and Zephyr it shall not be
reading a big block size to avoid "garbage" data.

Change-Id: I1c2a22db28bf0ada734563e40efd4f5749951273
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

show more ...

fix(intel): flush L1/L2/L3/Sys cache before HPS cold reset

This fix is to flush and invalidate the caches before cold reset.
Issue happen where Agilex5 hardware does not support the caches flush.
Th

fix(intel): flush L1/L2/L3/Sys cache before HPS cold reset

This fix is to flush and invalidate the caches before cold reset.
Issue happen where Agilex5 hardware does not support the caches flush.
Thus software workaround is needed.

Change-Id: Ibfeecbc611d238a069ca72f8b833f319e794cd38
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

show more ...

Merge "fix(intel): update Agilex5 BL2 init flow and other misc changes" into integration

Merge "feat(intel): update Agilex5 DDR and IOSSM driver" into integration

fix(intel): update Agilex5 BL2 init flow and other misc changes

BL2: Update BL2 init flow, Timer base address, avoid cache
flush of BL2 image descriptors
BL31: Remove re-init of CCU and other misc u

fix(intel): update Agilex5 BL2 init flow and other misc changes

BL2: Update BL2 init flow, Timer base address, avoid cache
flush of BL2 image descriptors
BL31: Remove re-init of CCU and other misc updates

Change-Id: I5f04901cc455c306209c83aad2377bbf7d8a1789
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

show more ...

feat(intel): update Agilex5 DDR and IOSSM driver

DDR and IOSSM driver code for Agilex5 platform,
initialize the DDR/IOSSM in BL2 EL3 early flow.

Change-Id: I3e4205171d9356190b60498cae322318520bb1c2

feat(intel): update Agilex5 DDR and IOSSM driver

DDR and IOSSM driver code for Agilex5 platform,
initialize the DDR/IOSSM in BL2 EL3 early flow.

Change-Id: I3e4205171d9356190b60498cae322318520bb1c2
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

show more ...

Merge changes Id85b2541,I4d253e2f into integration

* changes:
fix(intel): update system counter back to 400MHz
fix(intel): revert back to use L4 clock

Merge changes I548e3034,I65c7fd1b,I1cdacc0f,If9ac35af into integration

* changes:
feat(intel): support QSPI ECC Linux for Agilex
feat(intel): support QSPI ECC Linux for N5X
feat(intel): suppor

Merge changes I548e3034,I65c7fd1b,I1cdacc0f,If9ac35af into integration

* changes:
feat(intel): support QSPI ECC Linux for Agilex
feat(intel): support QSPI ECC Linux for N5X
feat(intel): support QSPI ECC Linux for Stratix10
feat(intel): add in QSPI ECC for Linux

show more ...

fix(intel): update system counter back to 400MHz

Due to design issue, updated system counter back to hardcoded 400MHz

Change-Id: Id85b2541880fac88b2a9a0a46b27b0a0da0eed6d
Signed-off-by: Jit Loon Li

fix(intel): update system counter back to 400MHz

Due to design issue, updated system counter back to hardcoded 400MHz

Change-Id: Id85b2541880fac88b2a9a0a46b27b0a0da0eed6d
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

show more ...

feat(intel): support QSPI ECC Linux for Agilex

Add QSPI ECC new opcodes for Linux to access to SDM register

Change-Id: I548e30340320ae2c2c9d60d20b218ee844516d64
Signed-off-by: Jit Loon Lim <jit.loo

feat(intel): support QSPI ECC Linux for Agilex

Add QSPI ECC new opcodes for Linux to access to SDM register

Change-Id: I548e30340320ae2c2c9d60d20b218ee844516d64
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

show more ...

Merge "fix(intel): fix hardcoded mpu frequency ticks" into integration