Merge "fix(intel): solve s10 warm reset issue" into integration

fix(intel): solve s10 warm reset issue

This is extension of the patch to fix the warm
reset issue in agilex refer to this commit 7f4fa931a.

The warm reset not able to trigger due to the system
not

fix(intel): solve s10 warm reset issue

This is extension of the patch to fix the warm
reset issue in agilex refer to this commit 7f4fa931a.

The warm reset not able to trigger due to the system
not able to detect the magic number. ATF only able
to solve for boot core. For secondary cores, Linux
need to update psci driver to WFI the cores in EL3.
Original Linux WFI is EL1.
Thus causing secondary cores not working.

Change-Id: Iee5e3f6d3334832fe432721fcf7b872534334988
Signed-off-by: Boon Khai Ng <boon.khai.ng@altera.com>

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Merge "fix(intel): update warm reset routine and bootscratch register usage" into integration

fix(intel): update warm reset routine and bootscratch register usage

Agilex5 platform:
Boot scratch COLD6 register is meant for Customer use only.
So, use Intel specific COLD3 register with [5:2]bit

fix(intel): update warm reset routine and bootscratch register usage

Agilex5 platform:
Boot scratch COLD6 register is meant for Customer use only.
So, use Intel specific COLD3 register with [5:2]bits to
determine the warm reset and SMP boot requests.
Also handle the unaligned DEVICE/IO memory store and load
in the assembly entrypoint startup code.

Agilex, Stratix10, N5X platforms:
Use only the LSB 4bits [3:0] of the boot scratch COLD6 register
to detect the warm reset request.

Change-Id: I4fd6e63fe0bd42ddcb4a3f81c7a7295bdc8ca65f
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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Merge "feat(intel): add build option for boot source" into integration

Merge "fix(intel): refactor SDMMC driver for Altera products" into integration

fix(intel): refactor SDMMC driver for Altera products

Refactor to be more robust. Removed duplicated and not used functions.
Add in ADMA read.

Change-Id: I1a5a00397ece6f9ccc5916225ab5317010b01b52
S

fix(intel): refactor SDMMC driver for Altera products

Refactor to be more robust. Removed duplicated and not used functions.
Add in ADMA read.

Change-Id: I1a5a00397ece6f9ccc5916225ab5317010b01b52
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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feat(intel): add build option for boot source

Existing boot source is hardcoded in socfpga_plat_def.h.
To change boot source, user need to update code.
Thus adding this will remove the code update n

feat(intel): add build option for boot source

Existing boot source is hardcoded in socfpga_plat_def.h.
To change boot source, user need to update code.
Thus adding this will remove the code update needed when
need to change boot source.

Also, it will have ARM_LINUX_KERNEL_AS_BL33 flag for each
platform in platform.mk. This will be easily to control
based on platform build.

Change-Id: I383beb8cbca5ec0f247221ad42796554adc3daae
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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Merge "fix(intel): update all the platforms hand-off data offset value" into integration

fix(intel): update all the platforms hand-off data offset value

Move the hand-off data offset value from the common
platform header file to each socfpga platform specific
header file.

Change-Id: Ic

fix(intel): update all the platforms hand-off data offset value

Move the hand-off data offset value from the common
platform header file to each socfpga platform specific
header file.

Change-Id: Icfe917f788814c329659c44e298cf05d6e3d0dd9
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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Merge "fix(intel): update preloaded_bl33_base for legacy product" into integration

fix(intel): update preloaded_bl33_base for legacy product

Update preloaded_bl33_base for legacy product for Yocto.

The Yocto Jenkins build was initially configured to build products
where the start

fix(intel): update preloaded_bl33_base for legacy product

Update preloaded_bl33_base for legacy product for Yocto.

The Yocto Jenkins build was initially configured to build products
where the starting of the DDR is from 0x0000 0000. And if there is
no NS_image_offset set, the Jenkins is not able to acquire the correct
address offset to boot up the system. However, in the direct OS boot,
there is no issue as the user shall always include the address offset
during the compilation phase. Otherwise, the code shall execute the
default address offset. Besides that, this also provides the
flexibility to user to customize their SoC design by not restricted
to the default address.

SDMMC block size. It was changed due to the need when boot to Linux.
Kernel.itb size is big thus we have to increase the available reading
block size. Otherwise for normal U-boot and Zephyr it shall not be
reading a big block size to avoid "garbage" data.

Change-Id: I1c2a22db28bf0ada734563e40efd4f5749951273
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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Merge "fix(intel): update Agilex5 BL2 init flow and other misc changes" into integration

fix(intel): update Agilex5 BL2 init flow and other misc changes

BL2: Update BL2 init flow, Timer base address, avoid cache
flush of BL2 image descriptors
BL31: Remove re-init of CCU and other misc u

fix(intel): update Agilex5 BL2 init flow and other misc changes

BL2: Update BL2 init flow, Timer base address, avoid cache
flush of BL2 image descriptors
BL31: Remove re-init of CCU and other misc updates

Change-Id: I5f04901cc455c306209c83aad2377bbf7d8a1789
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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Merge changes Id85b2541,I4d253e2f into integration

* changes:
fix(intel): update system counter back to 400MHz
fix(intel): revert back to use L4 clock

Merge changes I548e3034,I65c7fd1b,I1cdacc0f,If9ac35af into integration

* changes:
feat(intel): support QSPI ECC Linux for Agilex
feat(intel): support QSPI ECC Linux for N5X
feat(intel): suppor

Merge changes I548e3034,I65c7fd1b,I1cdacc0f,If9ac35af into integration

* changes:
feat(intel): support QSPI ECC Linux for Agilex
feat(intel): support QSPI ECC Linux for N5X
feat(intel): support QSPI ECC Linux for Stratix10
feat(intel): add in QSPI ECC for Linux

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fix(intel): update system counter back to 400MHz

Due to design issue, updated system counter back to hardcoded 400MHz

Change-Id: Id85b2541880fac88b2a9a0a46b27b0a0da0eed6d
Signed-off-by: Jit Loon Li

fix(intel): update system counter back to 400MHz

Due to design issue, updated system counter back to hardcoded 400MHz

Change-Id: Id85b2541880fac88b2a9a0a46b27b0a0da0eed6d
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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feat(intel): support QSPI ECC Linux for Stratix10

Add QSPI ECC new opcodes for Linux to access to SDM register

Change-Id: I1cdacc0f10dfa2a969f0bc5086277fd9081d02e2
Signed-off-by: Jit Loon Lim <jit.

feat(intel): support QSPI ECC Linux for Stratix10

Add QSPI ECC new opcodes for Linux to access to SDM register

Change-Id: I1cdacc0f10dfa2a969f0bc5086277fd9081d02e2
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>

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Merge "fix(intel): fix hardcoded mpu frequency ticks" into integration

fix(intel): fix hardcoded mpu frequency ticks

This patch is used to update the hardcoded mpu freq ticks
to obtain the freqq from the hardware setting itself.

Change-Id: I7b9eb49f2512b85fb477110f06a

fix(intel): fix hardcoded mpu frequency ticks

This patch is used to update the hardcoded mpu freq ticks
to obtain the freqq from the hardware setting itself.

Change-Id: I7b9eb49f2512b85fb477110f06ae86ef289aee58
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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Merge "feat(intel): restructure watchdog" into integration

Merge "feat(intel): increase bl2 size limit" into integration

feat(intel): increase bl2 size limit

There are several features included in BL2 causing the size getting
bigger for RELEASE mode. When build with DEBUG mode, the size will
be bigger thus causing BL2

feat(intel): increase bl2 size limit

There are several features included in BL2 causing the size getting
bigger for RELEASE mode. When build with DEBUG mode, the size will
be bigger thus causing BL2 image has exceeded its limits.

Change-Id: I7542f5ea001542450695d48e8126bcca8728d76a
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>

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feat(intel): restructure watchdog

This patch is to restructure watchdog.
Move platform dependent MACROs to individual platform socfpga_plat_def.
Common watchdog code file and header file will remain

feat(intel): restructure watchdog

This patch is to restructure watchdog.
Move platform dependent MACROs to individual platform socfpga_plat_def.
Common watchdog code file and header file will remain for those common
declaration.

Change-Id: Ibb640f08ac313bbad6d9295596cb8ff26e3e626d
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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Merge changes from topic "agilex5" into integration

* changes:
feat(intel): platform enablement for Agilex5 SoC FPGA
feat(intel): ccu driver for Agilex5 SoC FPGA
feat(intel): vab support for A

Merge changes from topic "agilex5" into integration

* changes:
feat(intel): platform enablement for Agilex5 SoC FPGA
feat(intel): ccu driver for Agilex5 SoC FPGA
feat(intel): vab support for Agilex5 SoC FPGA
feat(intel): sdmmc/nand/combo-phy/qspi driver for Agilex5 SoC FPGA
feat(intel): ddr driver for Agilex5 SoC FPGA
feat(intel): power manager for Agilex5 SoC FPGA
feat(intel): cold/warm reset and smp support for Agilex5 SoC FPGA
feat(intel): reset manager support for Agilex5 SoC FPGA
feat(intel): mailbox and SMC support for Agilex5 SoC FPGA
feat(intel): system manager support for Agilex5 SoC FPGA
feat(intel): memory controller support for Agilex5 SoC FPGA
feat(intel): clock manager support for Agilex5 SoC FPGA
feat(intel): mmc support for Agilex5 SoC FPGA
feat(intel): uart support for Agilex5 SoC FPGA
feat(intel): pinmux, peripheral and Handoff support for Agilex5 SoC FPGA

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