1f91c3cb1SSiva Durga Prasad Paladugu /*
2619bc13eSMichal Simek * Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved.
309ac1ca2SMaheedhar Bollapalli * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
4f91c3cb1SSiva Durga Prasad Paladugu *
5f91c3cb1SSiva Durga Prasad Paladugu * SPDX-License-Identifier: BSD-3-Clause
6f91c3cb1SSiva Durga Prasad Paladugu */
7f91c3cb1SSiva Durga Prasad Paladugu
809d40e0eSAntonio Nino Diaz #include <common/debug.h>
909d40e0eSAntonio Nino Diaz #include <lib/mmio.h>
100e9f54e5SMichal Simek #include <lib/xlat_tables/xlat_tables_v2.h>
1109d40e0eSAntonio Nino Diaz #include <plat/common/platform.h>
12f91c3cb1SSiva Durga Prasad Paladugu
13079c6e24SAkshay Belsare #include <plat_common.h>
14079c6e24SAkshay Belsare #include <plat_ipi.h>
15079c6e24SAkshay Belsare #include <plat_private.h>
16079c6e24SAkshay Belsare #include <pm_api_sys.h>
17079c6e24SAkshay Belsare #include <versal_def.h>
18079c6e24SAkshay Belsare
19079c6e24SAkshay Belsare uint32_t platform_id, platform_version;
2009ac1ca2SMaheedhar Bollapalli uint32_t cpu_clock;
21079c6e24SAkshay Belsare
22f91c3cb1SSiva Durga Prasad Paladugu /*
23f91c3cb1SSiva Durga Prasad Paladugu * Table of regions to map using the MMU.
24f91c3cb1SSiva Durga Prasad Paladugu * This doesn't include TZRAM as the 'mem_layout' argument passed to
25f91c3cb1SSiva Durga Prasad Paladugu * configure_mmu_elx() will give the available subset of that,
26f91c3cb1SSiva Durga Prasad Paladugu */
27f91c3cb1SSiva Durga Prasad Paladugu const mmap_region_t plat_versal_mmap[] = {
28f91c3cb1SSiva Durga Prasad Paladugu MAP_REGION_FLAT(DEVICE0_BASE, DEVICE0_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
29f91c3cb1SSiva Durga Prasad Paladugu MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
30f91c3cb1SSiva Durga Prasad Paladugu MAP_REGION_FLAT(CRF_BASE, CRF_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
31245d30efSMichal Simek MAP_REGION_FLAT(PLAT_ARM_CCI_BASE, PLAT_ARM_CCI_SIZE, MT_DEVICE | MT_RW |
325a8ffeabSTejas Patel MT_SECURE),
33f91c3cb1SSiva Durga Prasad Paladugu { 0 }
34f91c3cb1SSiva Durga Prasad Paladugu };
35f91c3cb1SSiva Durga Prasad Paladugu
plat_get_mmap(void)3651564354SPrasad Kummari const mmap_region_t *plat_get_mmap(void)
37f91c3cb1SSiva Durga Prasad Paladugu {
38f91c3cb1SSiva Durga Prasad Paladugu return plat_versal_mmap;
39f91c3cb1SSiva Durga Prasad Paladugu }
40f91c3cb1SSiva Durga Prasad Paladugu
versal_config_setup(void)41f91c3cb1SSiva Durga Prasad Paladugu void versal_config_setup(void)
42f91c3cb1SSiva Durga Prasad Paladugu {
43c73a90e5STejas Patel /* Configure IPI data for versal */
44c73a90e5STejas Patel versal_ipi_config_table_init();
45f91c3cb1SSiva Durga Prasad Paladugu }
46f91c3cb1SSiva Durga Prasad Paladugu
board_detection(void)47079c6e24SAkshay Belsare void board_detection(void)
48079c6e24SAkshay Belsare {
49079c6e24SAkshay Belsare uint32_t plat_info[2];
50079c6e24SAkshay Belsare
51079c6e24SAkshay Belsare if (pm_get_chipid(plat_info) != PM_RET_SUCCESS) {
52079c6e24SAkshay Belsare /* If the call is failed we cannot proceed with further
53079c6e24SAkshay Belsare * setup. TF-A to panic in this situation.
54079c6e24SAkshay Belsare */
55079c6e24SAkshay Belsare NOTICE("Failed to read the chip information");
56079c6e24SAkshay Belsare panic();
57079c6e24SAkshay Belsare }
58079c6e24SAkshay Belsare
59079c6e24SAkshay Belsare platform_id = FIELD_GET(PLATFORM_MASK, plat_info[1]);
60079c6e24SAkshay Belsare platform_version = FIELD_GET(PLATFORM_VERSION_MASK, plat_info[1]);
61*db827f99SAkshay Belsare
62*db827f99SAkshay Belsare if (platform_id == VERSAL_COSIM) {
63*db827f99SAkshay Belsare platform_id = VERSAL_QEMU;
64*db827f99SAkshay Belsare }
65079c6e24SAkshay Belsare }
66c1e84acaSPrasad Kummari
board_name_decode(void)6709ac1ca2SMaheedhar Bollapalli const char *board_name_decode(void)
6809ac1ca2SMaheedhar Bollapalli {
6909ac1ca2SMaheedhar Bollapalli const char *platform;
7009ac1ca2SMaheedhar Bollapalli
7109ac1ca2SMaheedhar Bollapalli switch (platform_id) {
7209ac1ca2SMaheedhar Bollapalli case VERSAL_SPP:
7309ac1ca2SMaheedhar Bollapalli platform = "IPP";
7409ac1ca2SMaheedhar Bollapalli break;
7509ac1ca2SMaheedhar Bollapalli case VERSAL_EMU:
7609ac1ca2SMaheedhar Bollapalli platform = "EMU";
7709ac1ca2SMaheedhar Bollapalli break;
7809ac1ca2SMaheedhar Bollapalli case VERSAL_QEMU:
7909ac1ca2SMaheedhar Bollapalli platform = "QEMU";
8009ac1ca2SMaheedhar Bollapalli break;
8109ac1ca2SMaheedhar Bollapalli case VERSAL_SILICON:
8209ac1ca2SMaheedhar Bollapalli platform = "SILICON";
8309ac1ca2SMaheedhar Bollapalli break;
8409ac1ca2SMaheedhar Bollapalli default:
8509ac1ca2SMaheedhar Bollapalli platform = "unknown";
8609ac1ca2SMaheedhar Bollapalli }
8709ac1ca2SMaheedhar Bollapalli
8809ac1ca2SMaheedhar Bollapalli return platform;
8909ac1ca2SMaheedhar Bollapalli }
9009ac1ca2SMaheedhar Bollapalli
get_uart_clk(void)91c1e84acaSPrasad Kummari uint32_t get_uart_clk(void)
92c1e84acaSPrasad Kummari {
9309ac1ca2SMaheedhar Bollapalli uint32_t uart_clock;
9409ac1ca2SMaheedhar Bollapalli
9509ac1ca2SMaheedhar Bollapalli switch (platform_id) {
9609ac1ca2SMaheedhar Bollapalli case VERSAL_SPP:
9709ac1ca2SMaheedhar Bollapalli uart_clock = 25000000;
9809ac1ca2SMaheedhar Bollapalli break;
9909ac1ca2SMaheedhar Bollapalli case VERSAL_EMU:
10009ac1ca2SMaheedhar Bollapalli uart_clock = 212000;
10109ac1ca2SMaheedhar Bollapalli break;
10209ac1ca2SMaheedhar Bollapalli case VERSAL_QEMU:
10309ac1ca2SMaheedhar Bollapalli case VERSAL_SILICON:
10409ac1ca2SMaheedhar Bollapalli uart_clock = 100000000;
10509ac1ca2SMaheedhar Bollapalli break;
10609ac1ca2SMaheedhar Bollapalli default:
10709ac1ca2SMaheedhar Bollapalli panic();
10809ac1ca2SMaheedhar Bollapalli }
10909ac1ca2SMaheedhar Bollapalli
11009ac1ca2SMaheedhar Bollapalli return uart_clock;
111c1e84acaSPrasad Kummari }
112