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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/display/rockchip/
H A Drockchip-vop.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/rockchip/rockchip-vop.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip SoC display controller (VOP)
10 VOP (Video Output Processor) is the display controller for the Rockchip
15 - Sandy Huang <hjc@rock-chips.com>
16 - Heiko Stuebner <heiko@sntech.de>
21 - rockchip,px30-vop-big
22 - rockchip,px30-vop-lit
[all …]
H A Drockchip-drm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only)
3 ---
4 $id: http://devicetree.org/schemas/display/rockchip/rockchip-drm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip DRM master device
10 - Sandy Huang <hjc@rock-chips.com>
11 - Heiko Stuebner <heiko@sntech.de>
14 The Rockchip DRM master device is a virtual device needed to list all
15 vop devices or other display interface nodes that comprise the
20 const: rockchip,display-subsystem
[all …]
H A Drockchip-backlight.txt1 Rockchip DRM backlight device
4 Rockchip display controller(see VOP bindings[0]) support CABC function,
5 and the CABC function required using VOP self pwm to control backlight,
10 - compatible: Should be "rockchip,drm-backlight"
14 [0]: Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt
15 [1]: Documentation/devicetree/bindings/leds/backlight/pwm-backlight.txt
20 compatible = "rockchip,drm-backlight";
23 brightness-levels = <0 4 8 16 32 64 128 255>;
24 default-brightness-level = <6>;
26 power-supply = <&vdd_bl_reg>;
[all …]
H A Drockchip-rgb.txt1 Rockchip RGB interface
5 - compatible: matching the soc type:
6 - "rockchip,px30-rgb";
7 - "rockchip,rk1808-rgb";
8 - "rockchip,rk3066-rgb";
9 - "rockchip,rk3128-rgb";
10 - "rockchip,rk3288-rgb";
11 - "rockchip,rk3308-rgb";
12 - "rockchip,rk3368-rgb";
13 - "rockchip,rv1108-rgb";
[all …]
/OK3568_Linux_fs/u-boot/drivers/video/drm/
H A Drockchip_crtc.c2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd
4 * SPDX-License-Identifier: GPL-2.0+
16 #include <dm/device-internal.h>
25 { .compatible = "rockchip-vp" },
30 .name = "rockchip-vp",
137 .compatible = "rockchip,rk3036-vop",
140 .compatible = "rockchip,rv1108-vop",
143 .compatible = "rockchip,rv1106-vop",
146 .compatible = "rockchip,rv1126-vop",
149 .compatible = "rockchip,rk3126-vop",
[all …]
H A Drockchip_vop.h2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd
4 * SPDX-License-Identifier: GPL-2.0+
13 #define VOP_REG_SUPPORT(vop, reg) \ argument
16 (reg.major == VOP_MAJOR(vop->version) && \
17 reg.begin_minor <= VOP_MINOR(vop->version) && \
18 reg.end_minor >= VOP_MINOR(vop->version))))
20 #define VOP_WIN_SUPPORT(vop, win, name) \ argument
21 VOP_REG_SUPPORT(vop, win->name)
23 #define VOP_CTRL_SUPPORT(vop, name) \ argument
24 VOP_REG_SUPPORT(vop, vop->ctrl->name)
[all …]
H A Drockchip_vop.c2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd
4 * SPDX-License-Identifier: GPL-2.0+
16 #include <linux/media-bus-format.h>
31 return us * mode->clock / mode->htotal / 1000; in us_to_vertical_line()
34 static inline void set_vop_mcu_rs(struct vop *vop, int v) in set_vop_mcu_rs() argument
36 if (dm_gpio_is_valid(&vop->mcu_rs_gpio)) in set_vop_mcu_rs()
37 dm_gpio_set_value(&vop->mcu_rs_gpio, v); in set_vop_mcu_rs()
39 VOP_CTRL_SET(vop, mcu_rs, v); in set_vop_mcu_rs()
113 static int rockchip_vop_init_gamma(struct vop *vop, struct display_state *state) in rockchip_vop_init_gamma() argument
115 struct crtc_state *crtc_state = &state->crtc_state; in rockchip_vop_init_gamma()
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/rockchip/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 tristate "DRM Support for Rockchip"
15 Choose this option if you have a Rockchip soc chipset.
24 bool "Rockchip DRM debug"
29 debug node: /d/dri/0/ff900000.vop/vop_dump/dump
30 cat /d/dri/0/ff900000.vop/vop_dump/dump get more help
31 the upper ff900000.vop is different at different SOC platform.
34 bool "Rockchip DRM direct show"
39 bool "Rockchip DRM self test case"
45 bool "Rockchip VOP driver"
[all …]
H A Drockchip_drm_vop.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
4 * Author:Mark Yao <mark.yao@rock-chips.com>
11 #include <linux/fixp-arith.h>
42 #include <dt-bindings/soc/rockchip-system-status.h>
44 #include <soc/rockchip/rockchip_dmc.h>
45 #include <soc/rockchip/rockchip-system-status.h>
55 #define VOP_REG_SUPPORT(vop, reg) \ argument
58 (reg.major == VOP_MAJOR(vop->version) && \
59 reg.begin_minor <= VOP_MINOR(vop->version) && \
[all …]
H A Drockchip_drm_debugfs.h1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
4 * Author: Sandy Huang <hjc@rock-chips.com>
11 * struct vop_dump_info - vop dump plane info structure
17 /* @win_id: vop hard win index */
19 /* @area_id: vop hard area index inside win */
40 * struct vop_dump_list - store all buffer info per frame
H A Drockchip_drm_drv.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
4 * Author:Mark Yao <mark.yao@rock-chips.com>
21 #include <soc/rockchip/rockchip_dmc.h>
23 #include "../panel/panel-simple.h"
59 #define DRM_FORMAT_NV30 fourcc_code('N', 'V', '3', '0') /* non-subsampled Cr:Cb plane */
158 * @vop_dump_status the status of vop dump control
159 * @vop_dump_list_head the list head of vop dump list
425 * Rockchip drm private crtc funcs.
433 * @regs_dump: dump vop current register config.
[all …]
H A Drockchip_vop_reg.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
4 * Author:Mark Yao <mark.yao@rock-chips.com>
29 VOP_REG_VER_MASK(off, _mask, s, false, 0, 0, -1)
32 VOP_REG_VER_MASK(off, _mask, s, true, 0, 0, -1)
89 DRM_FORMAT_YVYU, /* yuv422_8bit[YVYU] linear mode or non-Linear mode */
90 DRM_FORMAT_VYUY, /* yuv422_8bit[VYUY] linear mode or non-Linear mode */
91 DRM_FORMAT_YUYV, /* yuv422_8bit[YUYV] linear mode or non-Linear mode */
92 DRM_FORMAT_UYVY, /* yuv422_8bit[UYVY] linear mode or non-Linear mode */
189 .csc_mode = VOP_REG_VER(RK3288_WIN0_CTRL0, 0x3, 10, 3, 2, -1),
[all …]
H A Danalogix_dp-rockchip.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Rockchip SoC DP (Display Port) interface driver.
5 * Copyright (C) Fuzhou Rockchip Electronics Co., Ltd.
6 * Author: Andy Yan <andy.yan@rock-chips.com>
7 * Yakir Yang <ykk@rock-chips.com>
8 * Jeff Chen <jeff.chen@rock-chips.com>
54 * struct rockchip_dp_chip_data - splite the grf setting of kind of chips
109 if (!field->valid) in rockchip_grf_field_write()
112 mask = GENMASK(field->msb, field->lsb); in rockchip_grf_field_write()
113 val <<= field->lsb; in rockchip_grf_field_write()
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Drk628.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 // Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
4 #include <dt-bindings/reset/rk628-rgu.h>
5 #include <dt-bindings/clock/rk628-cgu.h>
8 rk628_xin_osc0_func: rk628-xin-osc0-func {
9 compatible = "fixed-clock";
10 #clock-cells = <0>;
11 clock-frequency = <24000000>;
12 clock-output-names = "rk628_xin_osc0_func";
15 rk628_xin_osc0_half: rk628-xin-osc0-half {
[all …]
H A Drk3188.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/clock/rk3188-cru.h>
10 #include <dt-bindings/power/rk3188-power.h>
14 compatible = "rockchip,rk3188";
24 #address-cells = <1>;
25 #size-cells = <0>;
26 enable-method = "rockchip,rk3066-smp";
30 compatible = "arm,cortex-a9";
[all …]
H A Drk3066a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/clock/rk3066a-cru.h>
10 #include <dt-bindings/power/rk3066-power.h>
14 compatible = "rockchip,rk3066a";
26 #address-cells = <1>;
27 #size-cells = <0>;
28 enable-method = "rockchip,rk3066-smp";
32 compatible = "arm,cortex-a9";
[all …]
/OK3568_Linux_fs/u-boot/drivers/video/rockchip/
H A Drk3288_vop.c4 * Copyright 2014 Rockchip Inc.
6 * SPDX-License-Identifier: GPL-2.0+
27 struct rk3288_vop *regs = priv->regs; in rk3288_set_pin_polarity()
29 /* The RK3328 VOP (v3.1) has its polarity configuration in ctrl0 */ in rk3288_set_pin_polarity()
30 clrsetbits_le32(&regs->dsp_ctrl0, in rk3288_set_pin_polarity()
40 /* lcdc(vop) iodomain select 1.8V */ in rk3288_set_io_vsel()
41 rk_setreg(&grf->io_vsel, 1 << 0); in rk3288_set_io_vsel()
60 if (!(gd->flags & GD_FLG_RELOC)) in rk3288_vop_probe()
63 /* Set the LCDC(vop) iodomain to 1.8V */ in rk3288_vop_probe()
66 /* Probe regulators required for the RK3288 VOP */ in rk3288_vop_probe()
[all …]
H A Drk3399_vop.c4 * Copyright 2014 Rockchip Inc.
6 * SPDX-License-Identifier: GPL-2.0+
24 struct rk3288_vop *regs = priv->regs; in rk3399_set_pin_polarity()
27 * The RK3399 VOPs (v3.5 and v3.6) require a per-mode setting of in rk3399_set_pin_polarity()
32 clrsetbits_le32(&regs->dsp_ctrl1, in rk3399_set_pin_polarity()
38 clrsetbits_le32(&regs->dsp_ctrl1, in rk3399_set_pin_polarity()
44 clrsetbits_le32(&regs->dsp_ctrl1, in rk3399_set_pin_polarity()
67 if (!(gd->flags & GD_FLG_RELOC)) in rk3399_vop_probe()
70 /* Probe regulators required for the RK3399 VOP */ in rk3399_vop_probe()
87 { .compatible = "rockchip,rk3399-vop-big",
[all …]
H A Drk3288_mipi.c2 * Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd
3 * Author: Eric Gao <eric.gao@rock-chips.com>
5 * SPDX-License-Identifier: GPL-2.0+
20 #include <dm/uclass-internal.h>
31 /* Select mipi dsi source, big or little vop */
35 struct rk3288_grf *grf = priv->grf; in rk_mipi_dsi_source_select()
39 switch (disp_uc_plat->source_id) { in rk_mipi_dsi_source_select()
41 rk_clrsetreg(&grf->soc_con6, RK3288_DSI0_LCDC_SEL_MASK, in rk_mipi_dsi_source_select()
46 rk_clrsetreg(&grf->soc_con6, RK3288_DSI0_LCDC_SEL_MASK, in rk_mipi_dsi_source_select()
51 debug("%s: Invalid VOP id\n", __func__); in rk_mipi_dsi_source_select()
[all …]
H A Drk3399_mipi.c2 * Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd
3 * Author: Eric Gao <eric.gao@rock-chips.com>
5 * SPDX-License-Identifier: GPL-2.0+
20 #include <dm/uclass-internal.h>
29 /* Select mipi dsi source, big or little vop */
33 struct rk3399_grf_regs *grf = priv->grf; in rk_mipi_dsi_source_select()
37 switch (disp_uc_plat->source_id) { in rk_mipi_dsi_source_select()
39 rk_clrsetreg(&grf->soc_con20, GRF_DSI0_VOP_SEL_MASK, in rk_mipi_dsi_source_select()
43 rk_clrsetreg(&grf->soc_con20, GRF_DSI0_VOP_SEL_MASK, in rk_mipi_dsi_source_select()
47 debug("%s: Invalid VOP id\n", __func__); in rk_mipi_dsi_source_select()
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/pwm/
H A Dpwm-rockchip.txt1 Rockchip PWM controller
4 - compatible: should be "rockchip,<name>-pwm"
5 "rockchip,rk2928-pwm": found on RK29XX,RK3066 and RK3188 SoCs
6 "rockchip,rk3288-pwm": found on RK3288 SOC
7 "rockchip,rv1108-pwm", "rockchip,rk3288-pwm": found on RV1108 SoC
8 "rockchip,vop-pwm": found integrated in VOP on RK3288 SoC
9 - reg: physical base address and length of the controller's registers
10 - clocks: See ../clock/clock-bindings.txt
11 - For older hardware (rk2928, rk3066, rk3188, rk3228, rk3288, rk3399):
12 - There is one clock that's used both to derive the functional clock
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/video/
H A Drockchip_lcdc.txt1 Device-Tree bindings for Rockchip SoC display controller (VOP / LCDC)
2 VOP (Video Output Process) / LCDC is the Display Controller for the
3 ROCKCHIP series of SoCs which transfers the image data from a video memory
7 - compatible: value should be one of the following
8 "rockchip,rk3288-lcdc"; /* for RK3288 SoCs */
9 "rockchip,rk3368-lcdc"; /* for RK3368 SoCs */
10 "rockchip,rk322x-lcdc"; /* for RK322X SoCs */
11 "rockchip,rk3399-lcdc"; /* for RK3399 SoCs */
12 - rockchip,prop: set the lcdc as primary or extend display.
13 - rochchip,pwr18: set the controller IO voltage,0 is 3.3v,1 is 1.8v.
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-rockchip/rk3588/
H A Dsyscon_rk3588.c2 * (C) Copyright 2021 Rockchip Electronics Co., Ltd
4 * SPDX-License-Identifier: GPL-2.0+
13 { .compatible = "rockchip,rk3588-sys-grf", .data = ROCKCHIP_SYSCON_GRF },
14 { .compatible = "rockchip,rk3588-vop-grf", .data = ROCKCHIP_SYSCON_VOP_GRF },
15 { .compatible = "rockchip,rk3588-vo-grf", .data = ROCKCHIP_SYSCON_VO_GRF },
16 { .compatible = "rockchip,pcie30-phy-grf", .data = ROCKCHIP_SYSCON_PCIE30_PHY_GRF },
17 { .compatible = "rockchip,rk3588-php-grf", .data = ROCKCHIP_SYSCON_PHP_GRF },
18 { .compatible = "rockchip,pipe-phy-grf", .data = ROCKCHIP_SYSCON_PIPE_PHY0_GRF },
19 { .compatible = "rockchip,pipe-phy-grf", .data = ROCKCHIP_SYSCON_PIPE_PHY1_GRF },
20 { .compatible = "rockchip,pipe-phy-grf", .data = ROCKCHIP_SYSCON_PIPE_PHY2_GRF },
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/
H A Drk3562-android.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
12 fiq-debugger {
13 compatible = "rockchip,fiq-debugger";
14 rockchip,serial-id = <0>;
15 rockchip,wake-irq = <0>;
17 rockchip,irq-mode-enable = <1>;
18 rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */
20 pinctrl-names = "default";
21 pinctrl-0 = <&uart0m0_xfer>;
[all …]
H A Drk3588s-evb3-lp4x-v10-rk630-bt656-to-cvbs.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
7 /dts-v1/;
9 #include <dt-bindings/display/media-bus-format.h>
10 #include "rk3588s-evb3-lp4x.dtsi"
11 #include "rk3588-android.dtsi"
14 model = "Rockchip RK3588S EVB3 LP4 V10 Board + Rockchip RK3588S EVB V10 Extboard1";
15 compatible = "rockchip,rk3588s-evb3-lp4x-v10-rk630-bt656-to-cvbs", "rockchip,rk3588";
24 clock-frequency = <100000>;
27 compatible = "rockchip,rk630";
[all …]

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