1*4882a593SmuzhiyunDevice-Tree bindings for Rockchip SoC display controller (VOP / LCDC) 2*4882a593SmuzhiyunVOP (Video Output Process) / LCDC is the Display Controller for the 3*4882a593SmuzhiyunROCKCHIP series of SoCs which transfers the image data from a video memory 4*4882a593Smuzhiyunbuffer to an external LCD interface. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunRequired properties: 7*4882a593Smuzhiyun- compatible: value should be one of the following 8*4882a593Smuzhiyun "rockchip,rk3288-lcdc"; /* for RK3288 SoCs */ 9*4882a593Smuzhiyun "rockchip,rk3368-lcdc"; /* for RK3368 SoCs */ 10*4882a593Smuzhiyun "rockchip,rk322x-lcdc"; /* for RK322X SoCs */ 11*4882a593Smuzhiyun "rockchip,rk3399-lcdc"; /* for RK3399 SoCs */ 12*4882a593Smuzhiyun- rockchip,prop: set the lcdc as primary or extend display. 13*4882a593Smuzhiyun- rochchip,pwr18: set the controller IO voltage,0 is 3.3v,1 is 1.8v. 14*4882a593Smuzhiyun- reg: physical base address and length of the LCDC registers set. 15*4882a593Smuzhiyun- interrupts: interrupt number to the cpu and interrupt proterties. 16*4882a593Smuzhiyun- pinctrl-names: must contain a "default" entry. 17*4882a593Smuzhiyun- pinctrl-0: pin control group to be used for this controller. 18*4882a593Smuzhiyun- pinctrl-1: pin control group to be used for gpio. 19*4882a593Smuzhiyun- clocks: must include clock specifiers corresponding to entries in the 20*4882a593Smuzhiyun clock-names property. 21*4882a593Smuzhiyun- clock-names: list of clock names sorted in the same order as the clocks 22*4882a593Smuzhiyun property.. 23*4882a593Smuzhiyun 24*4882a593SmuzhiyunOptional Properties: 25*4882a593Smuzhiyun- rockchip,debug: printk debug message. 26*4882a593Smuzhiyun- rockchip,mirror: the lcdc mirror function. 27*4882a593Smuzhiyun- lcd_en:lcd_en: contain power control for lcd. 28*4882a593Smuzhiyun - rockchip,power_type: power type,GPIO or REGULATOR. 29*4882a593Smuzhiyun - gpios: pin number for gpio. 30*4882a593Smuzhiyun - rockchip,delay: delay time after set power. 31*4882a593Smuzhiyun 32*4882a593SmuzhiyunExample: 33*4882a593Smuzhiyun 34*4882a593SmuzhiyunSoC specific DT entry: 35*4882a593Smuzhiyun lcdc1: lcdc@ff940000 { 36*4882a593Smuzhiyun compatible = "rockchip,rk3288-lcdc"; 37*4882a593Smuzhiyun rockchip,prop = <PRMRY>; 38*4882a593Smuzhiyun rochchip,pwr18 = <0>; 39*4882a593Smuzhiyun reg = <0xff940000 0x10000>; 40*4882a593Smuzhiyun interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 41*4882a593Smuzhiyun pinctrl-names = "default", "gpio"; 42*4882a593Smuzhiyun pinctrl-0 = <&lcdc0_lcdc>; 43*4882a593Smuzhiyun pinctrl-1 = <&lcdc0_gpio>; 44*4882a593Smuzhiyun status = "disabled"; 45*4882a593Smuzhiyun clocks = <&clk_gates15 7>, <&dclk_lcdc1>, <&clk_gates15 8>, <&pd_vop1>; 46*4882a593Smuzhiyun clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "pd_lcdc"; 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun 50*4882a593SmuzhiyunBoard specific DT entry: 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun&lcdc1 { 53*4882a593Smuzhiyun status = "okay"; 54*4882a593Smuzhiyun power_ctr: power_ctr { 55*4882a593Smuzhiyun rockchip,debug = <0>; 56*4882a593Smuzhiyun rockchip,mirror = <NO_MIRROR>; 57*4882a593Smuzhiyun lcd_en:lcd_en { 58*4882a593Smuzhiyun rockchip,power_type = <GPIO>; 59*4882a593Smuzhiyun gpios = <&gpio7 GPIO_A3 GPIO_ACTIVE_HIGH>; 60*4882a593Smuzhiyun rockchip,delay = <10>; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun lcd_cs:lcd_cs { 63*4882a593Smuzhiyun rockchip,power_type = <GPIO>; 64*4882a593Smuzhiyun gpios = <&gpio7 GPIO_A4 GPIO_ACTIVE_HIGH>; 65*4882a593Smuzhiyun rockchip,delay = <10>; 66*4882a593Smuzhiyun }; 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun}; 69*4882a593Smuzhiyun 70