1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
3*4882a593Smuzhiyun * Copyright (c) 2015 Google, Inc
4*4882a593Smuzhiyun * Copyright 2014 Rockchip Inc.
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <common.h>
10*4882a593Smuzhiyun #include <display.h>
11*4882a593Smuzhiyun #include <dm.h>
12*4882a593Smuzhiyun #include <regmap.h>
13*4882a593Smuzhiyun #include <video.h>
14*4882a593Smuzhiyun #include <asm/hardware.h>
15*4882a593Smuzhiyun #include <asm/io.h>
16*4882a593Smuzhiyun #include "rk_vop.h"
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
19*4882a593Smuzhiyun
rk3399_set_pin_polarity(struct udevice * dev,enum vop_modes mode,u32 polarity)20*4882a593Smuzhiyun static void rk3399_set_pin_polarity(struct udevice *dev,
21*4882a593Smuzhiyun enum vop_modes mode, u32 polarity)
22*4882a593Smuzhiyun {
23*4882a593Smuzhiyun struct rk_vop_priv *priv = dev_get_priv(dev);
24*4882a593Smuzhiyun struct rk3288_vop *regs = priv->regs;
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun /*
27*4882a593Smuzhiyun * The RK3399 VOPs (v3.5 and v3.6) require a per-mode setting of
28*4882a593Smuzhiyun * the polarity configuration (in ctrl1).
29*4882a593Smuzhiyun */
30*4882a593Smuzhiyun switch (mode) {
31*4882a593Smuzhiyun case VOP_MODE_HDMI:
32*4882a593Smuzhiyun clrsetbits_le32(®s->dsp_ctrl1,
33*4882a593Smuzhiyun M_RK3399_DSP_HDMI_POL,
34*4882a593Smuzhiyun V_RK3399_DSP_HDMI_POL(polarity));
35*4882a593Smuzhiyun break;
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun case VOP_MODE_EDP:
38*4882a593Smuzhiyun clrsetbits_le32(®s->dsp_ctrl1,
39*4882a593Smuzhiyun M_RK3399_DSP_EDP_POL,
40*4882a593Smuzhiyun V_RK3399_DSP_EDP_POL(polarity));
41*4882a593Smuzhiyun break;
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun case VOP_MODE_MIPI:
44*4882a593Smuzhiyun clrsetbits_le32(®s->dsp_ctrl1,
45*4882a593Smuzhiyun M_RK3399_DSP_MIPI_POL,
46*4882a593Smuzhiyun V_RK3399_DSP_MIPI_POL(polarity));
47*4882a593Smuzhiyun break;
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun case VOP_MODE_LVDS:
50*4882a593Smuzhiyun /* The RK3399 has neither parallel RGB nor LVDS output. */
51*4882a593Smuzhiyun default:
52*4882a593Smuzhiyun debug("%s: unsupported output mode %x\n", __func__, mode);
53*4882a593Smuzhiyun }
54*4882a593Smuzhiyun }
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun /*
57*4882a593Smuzhiyun * Try some common regulators. We should really get these from the
58*4882a593Smuzhiyun * device tree somehow.
59*4882a593Smuzhiyun */
60*4882a593Smuzhiyun static const char * const rk3399_regulator_names[] = {
61*4882a593Smuzhiyun "vcc33_lcd"
62*4882a593Smuzhiyun };
63*4882a593Smuzhiyun
rk3399_vop_probe(struct udevice * dev)64*4882a593Smuzhiyun static int rk3399_vop_probe(struct udevice *dev)
65*4882a593Smuzhiyun {
66*4882a593Smuzhiyun /* Before relocation we don't need to do anything */
67*4882a593Smuzhiyun if (!(gd->flags & GD_FLG_RELOC))
68*4882a593Smuzhiyun return 0;
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun /* Probe regulators required for the RK3399 VOP */
71*4882a593Smuzhiyun rk_vop_probe_regulators(dev, rk3399_regulator_names,
72*4882a593Smuzhiyun ARRAY_SIZE(rk3399_regulator_names));
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun return rk_vop_probe(dev);
75*4882a593Smuzhiyun }
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun struct rkvop_driverdata rk3399_lit_driverdata = {
78*4882a593Smuzhiyun .set_pin_polarity = rk3399_set_pin_polarity,
79*4882a593Smuzhiyun };
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun struct rkvop_driverdata rk3399_big_driverdata = {
82*4882a593Smuzhiyun .features = VOP_FEATURE_OUTPUT_10BIT,
83*4882a593Smuzhiyun .set_pin_polarity = rk3399_set_pin_polarity,
84*4882a593Smuzhiyun };
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun static const struct udevice_id rk3399_vop_ids[] = {
87*4882a593Smuzhiyun { .compatible = "rockchip,rk3399-vop-big",
88*4882a593Smuzhiyun .data = (ulong)&rk3399_big_driverdata },
89*4882a593Smuzhiyun { .compatible = "rockchip,rk3399-vop-lit",
90*4882a593Smuzhiyun .data = (ulong)&rk3399_lit_driverdata },
91*4882a593Smuzhiyun { }
92*4882a593Smuzhiyun };
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun static const struct video_ops rk3399_vop_ops = {
95*4882a593Smuzhiyun };
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun U_BOOT_DRIVER(rk3399_vop) = {
98*4882a593Smuzhiyun .name = "rk3399_vop",
99*4882a593Smuzhiyun .id = UCLASS_VIDEO,
100*4882a593Smuzhiyun .of_match = rk3399_vop_ids,
101*4882a593Smuzhiyun .ops = &rk3399_vop_ops,
102*4882a593Smuzhiyun .bind = rk_vop_bind,
103*4882a593Smuzhiyun .probe = rk3399_vop_probe,
104*4882a593Smuzhiyun .priv_auto_alloc_size = sizeof(struct rk_vop_priv),
105*4882a593Smuzhiyun };
106