1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2022 Rockchip Electronics Co., Ltd. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun/ { 8*4882a593Smuzhiyun chosen: chosen { 9*4882a593Smuzhiyun bootargs = "earlycon=uart8250,mmio32,0xff210000 console=ttyFIQ0"; 10*4882a593Smuzhiyun }; 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun fiq-debugger { 13*4882a593Smuzhiyun compatible = "rockchip,fiq-debugger"; 14*4882a593Smuzhiyun rockchip,serial-id = <0>; 15*4882a593Smuzhiyun rockchip,wake-irq = <0>; 16*4882a593Smuzhiyun /* If enable uart uses irq instead of fiq */ 17*4882a593Smuzhiyun rockchip,irq-mode-enable = <1>; 18*4882a593Smuzhiyun rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ 19*4882a593Smuzhiyun interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 20*4882a593Smuzhiyun pinctrl-names = "default"; 21*4882a593Smuzhiyun pinctrl-0 = <&uart0m0_xfer>; 22*4882a593Smuzhiyun status = "okay"; 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun firmware { 26*4882a593Smuzhiyun optee: optee { 27*4882a593Smuzhiyun compatible = "linaro,optee-tz"; 28*4882a593Smuzhiyun method = "smc"; 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun}; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun&vop { 34*4882a593Smuzhiyun support-multi-area; 35*4882a593Smuzhiyun}; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun&rng { 38*4882a593Smuzhiyun status = "okay"; 39*4882a593Smuzhiyun}; 40