1*4882a593Smuzhiyun /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
4*4882a593Smuzhiyun * Author: Sandy Huang <hjc@rock-chips.com>
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #ifndef ROCKCHIP_DRM_DEBUGFS_H
8*4882a593Smuzhiyun #define ROCKCHIP_DRM_DEBUGFS_H
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun /**
11*4882a593Smuzhiyun * struct vop_dump_info - vop dump plane info structure
12*4882a593Smuzhiyun *
13*4882a593Smuzhiyun * Store plane info used to write display data to /data/vop_buf/
14*4882a593Smuzhiyun *
15*4882a593Smuzhiyun */
16*4882a593Smuzhiyun struct vop_dump_info {
17*4882a593Smuzhiyun /* @win_id: vop hard win index */
18*4882a593Smuzhiyun u8 win_id;
19*4882a593Smuzhiyun /* @area_id: vop hard area index inside win */
20*4882a593Smuzhiyun u8 area_id;
21*4882a593Smuzhiyun /* @AFBC_flag: indicate the buffer compress by gpu or not */
22*4882a593Smuzhiyun bool AFBC_flag;
23*4882a593Smuzhiyun /* @yuv_format: indicate yuv format or not */
24*4882a593Smuzhiyun bool yuv_format;
25*4882a593Smuzhiyun /* @pitches: the buffer pitch size */
26*4882a593Smuzhiyun u32 pitches;
27*4882a593Smuzhiyun /* @height: the buffer pitch height */
28*4882a593Smuzhiyun u32 height;
29*4882a593Smuzhiyun /* @info: DRM format info */
30*4882a593Smuzhiyun const struct drm_format_info *format;
31*4882a593Smuzhiyun /* @offset: the buffer offset */
32*4882a593Smuzhiyun unsigned long offset;
33*4882a593Smuzhiyun /* @num_pages: the pages number */
34*4882a593Smuzhiyun unsigned long num_pages;
35*4882a593Smuzhiyun /* @pages: store the buffer all pages */
36*4882a593Smuzhiyun struct page **pages;
37*4882a593Smuzhiyun };
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun /**
40*4882a593Smuzhiyun * struct vop_dump_list - store all buffer info per frame
41*4882a593Smuzhiyun *
42*4882a593Smuzhiyun * one frame maybe multiple buffer, all will be stored here.
43*4882a593Smuzhiyun *
44*4882a593Smuzhiyun */
45*4882a593Smuzhiyun struct vop_dump_list {
46*4882a593Smuzhiyun struct list_head entry;
47*4882a593Smuzhiyun struct vop_dump_info dump_info;
48*4882a593Smuzhiyun };
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun enum vop_dump_status {
51*4882a593Smuzhiyun DUMP_DISABLE = 0,
52*4882a593Smuzhiyun DUMP_KEEP
53*4882a593Smuzhiyun };
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun #if defined(CONFIG_ROCKCHIP_DRM_DEBUG)
56*4882a593Smuzhiyun int rockchip_drm_add_dump_buffer(struct drm_crtc *crtc, struct dentry *root);
57*4882a593Smuzhiyun int rockchip_drm_dump_plane_buffer(struct vop_dump_info *dump_info, int frame_count);
58*4882a593Smuzhiyun int rockchip_drm_debugfs_add_color_bar(struct drm_crtc *crtc, struct dentry *root);
59*4882a593Smuzhiyun #else
60*4882a593Smuzhiyun static inline int
rockchip_drm_add_dump_buffer(struct drm_crtc * crtc,struct dentry * root)61*4882a593Smuzhiyun rockchip_drm_add_dump_buffer(struct drm_crtc *crtc, struct dentry *root)
62*4882a593Smuzhiyun {
63*4882a593Smuzhiyun return 0;
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun static inline int
rockchip_drm_dump_plane_buffer(struct vop_dump_info * dump_info,int frame_count)67*4882a593Smuzhiyun rockchip_drm_dump_plane_buffer(struct vop_dump_info *dump_info, int frame_count)
68*4882a593Smuzhiyun {
69*4882a593Smuzhiyun return 0;
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun static inline int
rockchip_drm_debugfs_add_color_bar(struct drm_crtc * crtc,struct dentry * root)73*4882a593Smuzhiyun rockchip_drm_debugfs_add_color_bar(struct drm_crtc *crtc, struct dentry *root)
74*4882a593Smuzhiyun {
75*4882a593Smuzhiyun return 0;
76*4882a593Smuzhiyun }
77*4882a593Smuzhiyun #endif
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun #endif
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