1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
4 * Author:Mark Yao <mark.yao@rock-chips.com>
5 */
6
7 #include <linux/component.h>
8 #include <linux/kernel.h>
9 #include <linux/of.h>
10 #include <linux/platform_device.h>
11
12 #include <drm/drm_fourcc.h>
13 #include <drm/drm_print.h>
14
15 #include "rockchip_drm_vop.h"
16 #include "rockchip_vop_reg.h"
17
18 #define VOP_REG_VER_MASK(off, _mask, s, _write_mask, _major, \
19 _begin_minor, _end_minor) \
20 {.offset = off, \
21 .mask = _mask, \
22 .shift = s, \
23 .write_mask = _write_mask, \
24 .major = _major, \
25 .begin_minor = _begin_minor, \
26 .end_minor = _end_minor,}
27
28 #define VOP_REG(off, _mask, s) \
29 VOP_REG_VER_MASK(off, _mask, s, false, 0, 0, -1)
30
31 #define VOP_REG_MASK(off, _mask, s) \
32 VOP_REG_VER_MASK(off, _mask, s, true, 0, 0, -1)
33
34 #define VOP_REG_VER(off, _mask, s, _major, _begin_minor, _end_minor) \
35 VOP_REG_VER_MASK(off, _mask, s, false, \
36 _major, _begin_minor, _end_minor)
37
38
39 static const uint32_t formats_win_full[] = {
40 DRM_FORMAT_XRGB8888,
41 DRM_FORMAT_ARGB8888,
42 DRM_FORMAT_XBGR8888,
43 DRM_FORMAT_ABGR8888,
44 DRM_FORMAT_RGB888,
45 DRM_FORMAT_BGR888,
46 DRM_FORMAT_RGB565,
47 DRM_FORMAT_BGR565,
48 DRM_FORMAT_NV12,
49 DRM_FORMAT_NV16,
50 DRM_FORMAT_NV24,
51 };
52
53 static const uint32_t formats_win_full_10bit[] = {
54 DRM_FORMAT_XRGB8888,
55 DRM_FORMAT_ARGB8888,
56 DRM_FORMAT_XBGR8888,
57 DRM_FORMAT_ABGR8888,
58 DRM_FORMAT_RGB888,
59 DRM_FORMAT_BGR888,
60 DRM_FORMAT_RGB565,
61 DRM_FORMAT_BGR565,
62 DRM_FORMAT_NV12,
63 DRM_FORMAT_NV16,
64 DRM_FORMAT_NV24,
65 DRM_FORMAT_NV15, /* yuv420_10bit linear mode, 2 plane, no padding */
66 #ifdef CONFIG_NO_GKI
67 DRM_FORMAT_NV20, /* yuv422_10bit linear mode, 2 plane, no padding */
68 DRM_FORMAT_NV30, /* yuv444_10bit linear mode, 2 plane, no padding */
69 #endif
70 };
71
72 static const uint32_t formats_win_full_10bit_yuyv[] = {
73 DRM_FORMAT_XRGB8888,
74 DRM_FORMAT_ARGB8888,
75 DRM_FORMAT_XBGR8888,
76 DRM_FORMAT_ABGR8888,
77 DRM_FORMAT_RGB888,
78 DRM_FORMAT_BGR888,
79 DRM_FORMAT_RGB565,
80 DRM_FORMAT_BGR565,
81 DRM_FORMAT_NV12, /* yuv420_8bit linear mode, 2 plane */
82 DRM_FORMAT_NV16, /* yuv422_8bit linear mode, 2 plane */
83 DRM_FORMAT_NV24, /* yuv444_8bit linear mode, 2 plane */
84 DRM_FORMAT_NV15, /* yuv420_10bit linear mode, 2 plane, no padding */
85 #ifdef CONFIG_NO_GKI
86 DRM_FORMAT_NV20, /* yuv422_10bit linear mode, 2 plane, no padding */
87 DRM_FORMAT_NV30, /* yuv444_10bit linear mode, 2 plane, no padding */
88 #endif
89 DRM_FORMAT_YVYU, /* yuv422_8bit[YVYU] linear mode or non-Linear mode */
90 DRM_FORMAT_VYUY, /* yuv422_8bit[VYUY] linear mode or non-Linear mode */
91 DRM_FORMAT_YUYV, /* yuv422_8bit[YUYV] linear mode or non-Linear mode */
92 DRM_FORMAT_UYVY, /* yuv422_8bit[UYVY] linear mode or non-Linear mode */
93 };
94
95 static const uint32_t formats_win_lite[] = {
96 DRM_FORMAT_XRGB8888,
97 DRM_FORMAT_ARGB8888,
98 DRM_FORMAT_XBGR8888,
99 DRM_FORMAT_ABGR8888,
100 DRM_FORMAT_RGB888,
101 DRM_FORMAT_BGR888,
102 DRM_FORMAT_RGB565,
103 DRM_FORMAT_BGR565,
104 };
105
106 static const uint64_t format_modifiers[] = {
107 DRM_FORMAT_MOD_LINEAR,
108 DRM_FORMAT_MOD_INVALID,
109 };
110
111 static const uint64_t format_modifiers_afbc[] = {
112 DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16),
113
114 DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
115 AFBC_FORMAT_MOD_SPARSE),
116
117 DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
118 AFBC_FORMAT_MOD_YTR),
119
120 DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
121 AFBC_FORMAT_MOD_CBR),
122
123 DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
124 AFBC_FORMAT_MOD_YTR |
125 AFBC_FORMAT_MOD_SPARSE),
126
127 DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
128 AFBC_FORMAT_MOD_CBR |
129 AFBC_FORMAT_MOD_SPARSE),
130
131 DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
132 AFBC_FORMAT_MOD_YTR |
133 AFBC_FORMAT_MOD_CBR),
134
135 DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
136 AFBC_FORMAT_MOD_YTR |
137 AFBC_FORMAT_MOD_CBR |
138 AFBC_FORMAT_MOD_SPARSE),
139
140 /* SPLIT mandates SPARSE, RGB modes mandates YTR */
141 DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
142 AFBC_FORMAT_MOD_YTR |
143 AFBC_FORMAT_MOD_SPARSE |
144 AFBC_FORMAT_MOD_SPLIT),
145
146 DRM_FORMAT_MOD_LINEAR,
147 DRM_FORMAT_MOD_INVALID,
148 };
149
150 static const struct vop_scl_extension rk3288_win_full_scl_ext = {
151 .cbcr_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 31),
152 .cbcr_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 30),
153 .cbcr_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 28),
154 .cbcr_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 26),
155 .cbcr_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 24),
156 .yrgb_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 23),
157 .yrgb_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 22),
158 .yrgb_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 20),
159 .yrgb_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 18),
160 .yrgb_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 16),
161 .line_load_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 15),
162 .cbcr_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0x7, 12),
163 .yrgb_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0xf, 8),
164 .vsd_cbcr_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 7),
165 .vsd_cbcr_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 6),
166 .vsd_yrgb_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 5),
167 .vsd_yrgb_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 4),
168 .bic_coe_sel = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 2),
169 .cbcr_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 1),
170 .yrgb_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 0),
171 .lb_mode = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 5),
172 };
173
174 static const struct vop_scl_regs rk3288_win_full_scl = {
175 .ext = &rk3288_win_full_scl_ext,
176 .scale_yrgb_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
177 .scale_yrgb_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
178 .scale_cbcr_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
179 .scale_cbcr_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
180 };
181
182 static const struct vop_win_phy rk3288_win01_data = {
183 .scl = &rk3288_win_full_scl,
184 .data_formats = formats_win_full_10bit,
185 .nformats = ARRAY_SIZE(formats_win_full_10bit),
186 .enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
187 .format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
188 .fmt_10 = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 4),
189 .csc_mode = VOP_REG_VER(RK3288_WIN0_CTRL0, 0x3, 10, 3, 2, -1),
190 .rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
191 .xmirror = VOP_REG_VER(RK3368_WIN0_CTRL0, 0x1, 21, 3, 2, -1),
192 .ymirror = VOP_REG_VER(RK3368_WIN0_CTRL0, 0x1, 22, 3, 2, -1),
193 .act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
194 .dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0),
195 .dsp_st = VOP_REG(RK3288_WIN0_DSP_ST, 0x1fff1fff, 0),
196 .yrgb_mst = VOP_REG(RK3288_WIN0_YRGB_MST, 0xffffffff, 0),
197 .uv_mst = VOP_REG(RK3288_WIN0_CBR_MST, 0xffffffff, 0),
198 .yrgb_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 0),
199 .uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16),
200 .src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xffff, 0),
201 .global_alpha_val = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xff, 16),
202 .dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xffffffff, 0),
203 .channel = VOP_REG_VER(RK3288_WIN0_CTRL2, 0xff, 0, 3, 8, 8),
204 };
205
206 static const struct vop_win_phy rk3288_win23_data = {
207 .data_formats = formats_win_lite,
208 .nformats = ARRAY_SIZE(formats_win_lite),
209 .gate = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 0),
210 .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 4),
211 .format = VOP_REG(RK3288_WIN2_CTRL0, 0x7, 1),
212 .rb_swap = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 12),
213 .dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO0, 0x0fff0fff, 0),
214 .dsp_st = VOP_REG(RK3288_WIN2_DSP_ST0, 0x1fff1fff, 0),
215 .yrgb_mst = VOP_REG(RK3288_WIN2_MST0, 0xffffffff, 0),
216 .yrgb_vir = VOP_REG(RK3288_WIN2_VIR0_1, 0x1fff, 0),
217 .src_alpha_ctl = VOP_REG(RK3288_WIN2_SRC_ALPHA_CTRL, 0xffff, 0),
218 .global_alpha_val = VOP_REG(RK3288_WIN2_SRC_ALPHA_CTRL, 0xff, 16),
219 .dst_alpha_ctl = VOP_REG(RK3288_WIN2_DST_ALPHA_CTRL, 0xffffffff, 0),
220 };
221
222 static const struct vop_win_phy rk3288_area1_data = {
223 .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 5),
224 .dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO1, 0x0fff0fff, 0),
225 .dsp_st = VOP_REG(RK3288_WIN2_DSP_ST1, 0x1fff1fff, 0),
226 .yrgb_mst = VOP_REG(RK3288_WIN2_MST1, 0xffffffff, 0),
227 .yrgb_vir = VOP_REG(RK3288_WIN2_VIR0_1, 0x1fff, 16),
228 };
229
230 static const struct vop_win_phy rk3288_area2_data = {
231 .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 6),
232 .dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO2, 0x0fff0fff, 0),
233 .dsp_st = VOP_REG(RK3288_WIN2_DSP_ST2, 0x1fff1fff, 0),
234 .yrgb_mst = VOP_REG(RK3288_WIN2_MST2, 0xffffffff, 0),
235 .yrgb_vir = VOP_REG(RK3288_WIN2_VIR2_3, 0x1fff, 0),
236 };
237
238 static const struct vop_win_phy rk3288_area3_data = {
239 .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 7),
240 .dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO3, 0x0fff0fff, 0),
241 .dsp_st = VOP_REG(RK3288_WIN2_DSP_ST3, 0x1fff1fff, 0),
242 .yrgb_mst = VOP_REG(RK3288_WIN2_MST3, 0xffffffff, 0),
243 .yrgb_vir = VOP_REG(RK3288_WIN2_VIR2_3, 0x1fff, 16),
244 };
245
246 static const struct vop_win_phy *rk3288_area_data[] = {
247 &rk3288_area1_data,
248 &rk3288_area2_data,
249 &rk3288_area3_data
250 };
251
252 static const struct vop_ctrl rk3288_ctrl_data = {
253 .version = VOP_REG(RK3288_VERSION_INFO, 0xffff, 16),
254 .standby = VOP_REG(RK3288_SYS_CTRL, 0x1, 22),
255 .dma_stop = VOP_REG(RK3288_SYS_CTRL, 0x1, 21),
256 .axi_outstanding_max_num = VOP_REG(RK3288_SYS_CTRL1, 0x1f, 13),
257 .axi_max_outstanding_en = VOP_REG(RK3288_SYS_CTRL1, 0x1, 12),
258 .reg_done_frm = VOP_REG_VER(RK3288_SYS_CTRL1, 0x1, 24, 3, 5, -1),
259 .htotal_pw = VOP_REG(RK3288_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
260 .hact_st_end = VOP_REG(RK3288_DSP_HACT_ST_END, 0x1fff1fff, 0),
261 .vtotal_pw = VOP_REG(RK3288_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
262 .vact_st_end = VOP_REG(RK3288_DSP_VACT_ST_END, 0x1fff1fff, 0),
263 .vact_st_end_f1 = VOP_REG(RK3288_DSP_VACT_ST_END_F1, 0x1fff1fff, 0),
264 .vs_st_end_f1 = VOP_REG(RK3288_DSP_VS_ST_END_F1, 0x1fff1fff, 0),
265 .hpost_st_end = VOP_REG(RK3288_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
266 .vpost_st_end = VOP_REG(RK3288_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
267 .vpost_st_end_f1 = VOP_REG(RK3288_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0),
268 .post_scl_factor = VOP_REG(RK3288_POST_SCL_FACTOR_YRGB, 0xffffffff, 0),
269 .post_scl_ctrl = VOP_REG(RK3288_POST_SCL_CTRL, 0x3, 0),
270
271 .dsp_interlace = VOP_REG(RK3288_DSP_CTRL0, 0x1, 10),
272 .auto_gate_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 23),
273 .dsp_layer_sel = VOP_REG(RK3288_DSP_CTRL1, 0xff, 8),
274 .post_lb_mode = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 18, 3, 2, -1),
275 .global_regdone_en = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 11, 3, 2, -1),
276 .overlay_mode = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 16, 3, 2, -1),
277 .core_dclk_div = VOP_REG_VER(RK3366_DSP_CTRL0, 0x1, 4, 3, 4, -1),
278 .p2i_en = VOP_REG_VER(RK3366_DSP_CTRL0, 0x1, 5, 3, 4, -1),
279 .dclk_ddr = VOP_REG_VER(RK3288_DSP_CTRL0, 0x1, 8, 3, 1, -1),
280 .dp_en = VOP_REG_VER(RK3399_SYS_CTRL, 0x1, 11, 3, 5, -1),
281 .hdmi_dclk_out_en = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 11, 3, 1, 1),
282 .rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12),
283 .hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13),
284 .edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14),
285 .mipi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 15),
286 .mipi_dual_channel_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 3),
287 .data01_swap = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 17, 3, 5, -1),
288 .dclk_pol = VOP_REG_VER(RK3288_DSP_CTRL0, 0x1, 7, 3, 0, 1),
289 .pin_pol = VOP_REG_VER(RK3288_DSP_CTRL0, 0x7, 4, 3, 0, 1),
290 .dp_dclk_pol = VOP_REG_VER(RK3399_DSP_CTRL1, 0x1, 19, 3, 5, -1),
291 .dp_pin_pol = VOP_REG_VER(RK3399_DSP_CTRL1, 0x7, 16, 3, 5, -1),
292 .rgb_dclk_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x1, 19, 3, 2, -1),
293 .rgb_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x7, 16, 3, 2, -1),
294 .tve_dclk_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 24),
295 .tve_dclk_pol = VOP_REG(RK3288_SYS_CTRL, 0x1, 25),
296 .tve_sw_mode = VOP_REG(RK3288_SYS_CTRL, 0x1, 26),
297 .sw_uv_offset_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 27),
298 .sw_genlock = VOP_REG(RK3288_SYS_CTRL, 0x1, 28),
299 .hdmi_dclk_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x1, 23, 3, 2, -1),
300 .hdmi_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x7, 20, 3, 2, -1),
301 .edp_dclk_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x1, 27, 3, 2, -1),
302 .edp_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x7, 24, 3, 2, -1),
303 .mipi_dclk_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x1, 31, 3, 2, -1),
304 .mipi_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x7, 28, 3, 2, -1),
305
306 .dither_down_sel = VOP_REG(RK3288_DSP_CTRL1, 0x1, 4),
307 .dither_down_mode = VOP_REG(RK3288_DSP_CTRL1, 0x1, 3),
308 .dither_down_en = VOP_REG(RK3288_DSP_CTRL1, 0x1, 2),
309 .pre_dither_down_en = VOP_REG(RK3288_DSP_CTRL1, 0x1, 1),
310 .dither_up_en = VOP_REG(RK3288_DSP_CTRL1, 0x1, 6),
311
312 .dsp_out_yuv = VOP_REG_VER(RK3399_POST_SCL_CTRL, 0x1, 2, 3, 5, -1),
313 .dsp_data_swap = VOP_REG(RK3288_DSP_CTRL0, 0x1f, 12),
314 .dsp_bg_swap = VOP_REG(RK3288_DSP_CTRL0, 0x1, 12),
315 .dsp_rb_swap = VOP_REG(RK3288_DSP_CTRL0, 0x1, 13),
316 .dsp_rg_swap = VOP_REG(RK3288_DSP_CTRL0, 0x1, 14),
317 .dsp_delta_swap = VOP_REG(RK3288_DSP_CTRL0, 0x1, 15),
318 .dsp_dummy_swap = VOP_REG(RK3288_DSP_CTRL0, 0x1, 16),
319 .dsp_ccir656_avg = VOP_REG(RK3288_DSP_CTRL0, 0x1, 20),
320 .dsp_blank = VOP_REG(RK3288_DSP_CTRL0, 0x3, 18),
321 .update_gamma_lut = VOP_REG_VER(RK3288_DSP_CTRL1, 0x1, 7, 3, 5, -1),
322 .lut_buffer_index = VOP_REG_VER(RK3399_DBG_POST_REG1, 0x1, 1, 3, 5, -1),
323 .dsp_lut_en = VOP_REG(RK3288_DSP_CTRL1, 0x1, 0),
324 .out_mode = VOP_REG(RK3288_DSP_CTRL0, 0xf, 0),
325
326 .afbdc_rstn = VOP_REG_VER(RK3399_AFBCD0_CTRL, 0x1, 3, 3, 5, -1),
327 .afbdc_en = VOP_REG_VER(RK3399_AFBCD0_CTRL, 0x1, 0, 3, 5, -1),
328 .afbdc_sel = VOP_REG_VER(RK3399_AFBCD0_CTRL, 0x3, 1, 3, 5, -1),
329 .afbdc_format = VOP_REG_VER(RK3399_AFBCD0_CTRL, 0x1f, 16, 3, 5, -1),
330 .afbdc_hreg_block_split = VOP_REG_VER(RK3399_AFBCD0_CTRL,
331 0x1, 21, 3, 5, -1),
332 .afbdc_hdr_ptr = VOP_REG_VER(RK3399_AFBCD0_HDR_PTR, 0xffffffff,
333 0, 3, 5, -1),
334 .afbdc_pic_size = VOP_REG_VER(RK3399_AFBCD0_PIC_SIZE, 0xffffffff,
335 0, 3, 5, -1),
336 .bcsh_brightness = VOP_REG(RK3288_BCSH_BCS, 0xff, 0),
337 .bcsh_contrast = VOP_REG(RK3288_BCSH_BCS, 0x1ff, 8),
338 .bcsh_sat_con = VOP_REG(RK3288_BCSH_BCS, 0x3ff, 20),
339 .bcsh_out_mode = VOP_REG(RK3288_BCSH_BCS, 0x3, 30),
340 .bcsh_sin_hue = VOP_REG(RK3288_BCSH_H, 0x1ff, 0),
341 .bcsh_cos_hue = VOP_REG(RK3288_BCSH_H, 0x1ff, 16),
342 .bcsh_r2y_csc_mode = VOP_REG_VER(RK3368_BCSH_CTRL, 0x1, 6, 3, 1, -1),
343 .bcsh_r2y_en = VOP_REG_VER(RK3368_BCSH_CTRL, 0x1, 4, 3, 1, -1),
344 .bcsh_y2r_csc_mode = VOP_REG_VER(RK3368_BCSH_CTRL, 0x3, 2, 3, 1, -1),
345 .bcsh_y2r_en = VOP_REG_VER(RK3368_BCSH_CTRL, 0x1, 0, 3, 1, -1),
346 .bcsh_color_bar = VOP_REG(RK3288_BCSH_COLOR_BAR, 0xffffff, 8),
347 .bcsh_en = VOP_REG(RK3288_BCSH_COLOR_BAR, 0x1, 0),
348
349 .xmirror = VOP_REG(RK3288_DSP_CTRL0, 0x1, 22),
350 .ymirror = VOP_REG(RK3288_DSP_CTRL0, 0x1, 23),
351
352 .dsp_background = VOP_REG(RK3288_DSP_BG, 0xffffffff, 0),
353
354 .cfg_done = VOP_REG(RK3288_REG_CFG_DONE, 0x1, 0),
355 };
356
357 /*
358 * Note: rk3288 has a dedicated 'cursor' window, however, that window requires
359 * special support to get alpha blending working. For now, just use overlay
360 * window 3 for the drm cursor.
361 *
362 */
363 static const struct vop_win_data rk3288_vop_win_data[] = {
364 { .base = 0x00, .phy = &rk3288_win01_data,
365 .type = DRM_PLANE_TYPE_PRIMARY },
366 { .base = 0x40, .phy = &rk3288_win01_data,
367 .type = DRM_PLANE_TYPE_OVERLAY },
368 { .base = 0x00, .phy = &rk3288_win23_data,
369 .type = DRM_PLANE_TYPE_OVERLAY,
370 .area = rk3288_area_data,
371 .area_size = ARRAY_SIZE(rk3288_area_data), },
372 { .base = 0x50, .phy = &rk3288_win23_data,
373 .type = DRM_PLANE_TYPE_CURSOR,
374 .area = rk3288_area_data,
375 .area_size = ARRAY_SIZE(rk3288_area_data), },
376 };
377
378 static const int rk3288_vop_intrs[] = {
379 DSP_HOLD_VALID_INTR,
380 FS_INTR,
381 LINE_FLAG_INTR,
382 BUS_ERROR_INTR,
383 };
384
385 static const struct vop_intr rk3288_vop_intr = {
386 .intrs = rk3288_vop_intrs,
387 .nintrs = ARRAY_SIZE(rk3288_vop_intrs),
388 .line_flag_num[0] = VOP_REG(RK3288_INTR_CTRL0, 0x1fff, 12),
389 .status = VOP_REG(RK3288_INTR_CTRL0, 0xf, 0),
390 .enable = VOP_REG(RK3288_INTR_CTRL0, 0xf, 4),
391 .clear = VOP_REG(RK3288_INTR_CTRL0, 0xf, 8),
392 };
393
394 static const struct vop_grf_ctrl rk3288_vop_big_grf_ctrl = {
395 .grf_dclk_inv = VOP_REG(RK3288_GRF_SOC_CON15, 0x1, 13),
396 };
397
398 static const struct vop_grf_ctrl rk3288_vop_lit_grf_ctrl = {
399 .grf_dclk_inv = VOP_REG(RK3288_GRF_SOC_CON15, 0x1, 15),
400 };
401
402 static const struct vop_data rk3288_vop_big = {
403 .soc_id = 0x3288,
404 .vop_id = 0,
405 .version = VOP_VERSION(3, 0),
406 .feature = VOP_FEATURE_OUTPUT_10BIT | VOP_FEATURE_ALPHA_SCALE | VOP_FEATURE_OVERSCAN,
407 .max_input = {4096, 8192},
408 .max_output = {3840, 2160},
409 .intr = &rk3288_vop_intr,
410 .grf_ctrl = &rk3288_vop_big_grf_ctrl,
411 .ctrl = &rk3288_ctrl_data,
412 .win = rk3288_vop_win_data,
413 .win_size = ARRAY_SIZE(rk3288_vop_win_data),
414 };
415
416 static const struct vop_data rk3288_vop_lit = {
417 .soc_id = 0x3288,
418 .vop_id = 1,
419 .version = VOP_VERSION(3, 0),
420 .feature = VOP_FEATURE_OUTPUT_10BIT | VOP_FEATURE_ALPHA_SCALE | VOP_FEATURE_OVERSCAN,
421 .max_input = {4096, 8192},
422 .max_output = {2560, 1600},
423 .intr = &rk3288_vop_intr,
424 .grf_ctrl = &rk3288_vop_lit_grf_ctrl,
425 .ctrl = &rk3288_ctrl_data,
426 .win = rk3288_vop_win_data,
427 .win_size = ARRAY_SIZE(rk3288_vop_win_data),
428 };
429
430 static const int rk3368_vop_intrs[] = {
431 FS_INTR,
432 FS_NEW_INTR,
433 ADDR_SAME_INTR,
434 LINE_FLAG_INTR,
435 LINE_FLAG1_INTR,
436 BUS_ERROR_INTR,
437 WIN0_EMPTY_INTR,
438 WIN1_EMPTY_INTR,
439 WIN2_EMPTY_INTR,
440 WIN3_EMPTY_INTR,
441 HWC_EMPTY_INTR,
442 POST_BUF_EMPTY_INTR,
443 FS_FIELD_INTR,
444 DSP_HOLD_VALID_INTR,
445 };
446
447 static const struct vop_intr rk3368_vop_intr = {
448 .intrs = rk3368_vop_intrs,
449 .nintrs = ARRAY_SIZE(rk3368_vop_intrs),
450 .line_flag_num[0] = VOP_REG(RK3368_LINE_FLAG, 0xffff, 0),
451 .line_flag_num[1] = VOP_REG(RK3368_LINE_FLAG, 0xffff, 16),
452 .status = VOP_REG_MASK(RK3368_INTR_STATUS, 0x3fff, 0),
453 .enable = VOP_REG_MASK(RK3368_INTR_EN, 0x3fff, 0),
454 .clear = VOP_REG_MASK(RK3368_INTR_CLEAR, 0x3fff, 0),
455 };
456
457 static const struct vop_win_phy rk3368_win23_data = {
458 .data_formats = formats_win_lite,
459 .nformats = ARRAY_SIZE(formats_win_lite),
460 .gate = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 0),
461 .enable = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 4),
462 .format = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 5),
463 .ymirror = VOP_REG(RK3368_WIN2_CTRL1, 0x1, 15),
464 .rb_swap = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 20),
465 .dsp_info = VOP_REG(RK3368_WIN2_DSP_INFO0, 0x0fff0fff, 0),
466 .dsp_st = VOP_REG(RK3368_WIN2_DSP_ST0, 0x1fff1fff, 0),
467 .yrgb_mst = VOP_REG(RK3368_WIN2_MST0, 0xffffffff, 0),
468 .yrgb_vir = VOP_REG(RK3368_WIN2_VIR0_1, 0x1fff, 0),
469 .src_alpha_ctl = VOP_REG(RK3368_WIN2_SRC_ALPHA_CTRL, 0xffff, 0),
470 .global_alpha_val = VOP_REG(RK3368_WIN2_SRC_ALPHA_CTRL, 0xff, 16),
471 .dst_alpha_ctl = VOP_REG(RK3368_WIN2_DST_ALPHA_CTRL, 0xffffffff, 0),
472 .color_key = VOP_REG(RK3368_WIN2_COLOR_KEY, 0xffffff, 0),
473 .color_key_en = VOP_REG(RK3368_WIN2_COLOR_KEY, 0x1, 24),
474 };
475
476 static const struct vop_win_phy rk3368_area1_data = {
477 .enable = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 8),
478 .format = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 9),
479 .rb_swap = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 23),
480 .dsp_info = VOP_REG(RK3368_WIN2_DSP_INFO1, 0x0fff0fff, 0),
481 .dsp_st = VOP_REG(RK3368_WIN2_DSP_ST1, 0x1fff1fff, 0),
482 .yrgb_mst = VOP_REG(RK3368_WIN2_MST1, 0xffffffff, 0),
483 .yrgb_vir = VOP_REG(RK3368_WIN2_VIR0_1, 0x1fff, 16),
484 };
485
486 static const struct vop_win_phy rk3368_area2_data = {
487 .enable = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 12),
488 .format = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 13),
489 .rb_swap = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 26),
490 .dsp_info = VOP_REG(RK3368_WIN2_DSP_INFO2, 0x0fff0fff, 0),
491 .dsp_st = VOP_REG(RK3368_WIN2_DSP_ST2, 0x1fff1fff, 0),
492 .yrgb_mst = VOP_REG(RK3368_WIN2_MST2, 0xffffffff, 0),
493 .yrgb_vir = VOP_REG(RK3368_WIN2_VIR2_3, 0x1fff, 0),
494 };
495
496 static const struct vop_win_phy rk3368_area3_data = {
497 .enable = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 16),
498 .format = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 17),
499 .rb_swap = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 29),
500 .dsp_info = VOP_REG(RK3368_WIN2_DSP_INFO3, 0x0fff0fff, 0),
501 .dsp_st = VOP_REG(RK3368_WIN2_DSP_ST3, 0x1fff1fff, 0),
502 .yrgb_mst = VOP_REG(RK3368_WIN2_MST3, 0xffffffff, 0),
503 .yrgb_vir = VOP_REG(RK3368_WIN2_VIR2_3, 0x1fff, 16),
504 };
505
506 static const struct vop_win_phy *rk3368_area_data[] = {
507 &rk3368_area1_data,
508 &rk3368_area2_data,
509 &rk3368_area3_data
510 };
511
512 static const struct vop_win_data rk3368_vop_win_data[] = {
513 { .base = 0x00, .phy = &rk3288_win01_data,
514 .type = DRM_PLANE_TYPE_PRIMARY },
515 { .base = 0x40, .phy = &rk3288_win01_data,
516 .type = DRM_PLANE_TYPE_OVERLAY },
517 { .base = 0x00, .phy = &rk3368_win23_data,
518 .type = DRM_PLANE_TYPE_OVERLAY,
519 .area = rk3368_area_data,
520 .area_size = ARRAY_SIZE(rk3368_area_data), },
521 { .base = 0x50, .phy = &rk3368_win23_data,
522 .type = DRM_PLANE_TYPE_CURSOR,
523 .area = rk3368_area_data,
524 .area_size = ARRAY_SIZE(rk3368_area_data), },
525 };
526
527 static const struct vop_data rk3368_vop = {
528 .soc_id = 0x3368,
529 .vop_id = 0,
530 .version = VOP_VERSION(3, 2),
531 .feature = VOP_FEATURE_ALPHA_SCALE | VOP_FEATURE_OVERSCAN,
532 .max_input = {4096, 8192},
533 .max_output = {4096, 2160},
534 .intr = &rk3368_vop_intr,
535 .ctrl = &rk3288_ctrl_data,
536 .win = rk3368_vop_win_data,
537 .win_size = ARRAY_SIZE(rk3368_vop_win_data),
538 };
539
540 static const struct vop_intr rk3366_vop_intr = {
541 .intrs = rk3368_vop_intrs,
542 .nintrs = ARRAY_SIZE(rk3368_vop_intrs),
543 .line_flag_num[0] = VOP_REG(RK3366_LINE_FLAG, 0xffff, 0),
544 .line_flag_num[1] = VOP_REG(RK3366_LINE_FLAG, 0xffff, 16),
545 .status = VOP_REG_MASK(RK3366_INTR_STATUS0, 0xffff, 0),
546 .enable = VOP_REG_MASK(RK3366_INTR_EN0, 0xffff, 0),
547 .clear = VOP_REG_MASK(RK3366_INTR_CLEAR0, 0xffff, 0),
548 };
549
550 static const struct vop_grf_ctrl rk3368_vop_grf_ctrl = {
551 .grf_dclk_inv = VOP_REG(RK3368_GRF_SOC_CON6, 0x1, 5),
552 };
553
554 static const struct vop_data rk3366_vop = {
555 .soc_id = 0x3366,
556 .vop_id = 0,
557 .version = VOP_VERSION(3, 4),
558 .feature = VOP_FEATURE_ALPHA_SCALE | VOP_FEATURE_OVERSCAN,
559 .max_input = {4096, 8192},
560 .max_output = {4096, 2160},
561 .intr = &rk3366_vop_intr,
562 .grf_ctrl = &rk3368_vop_grf_ctrl,
563 .ctrl = &rk3288_ctrl_data,
564 .win = rk3368_vop_win_data,
565 .win_size = ARRAY_SIZE(rk3368_vop_win_data),
566 };
567
568 static const uint32_t vop_csc_y2r_bt601[] = {
569 0x00000400, 0x0400059c, 0xfd25fea0, 0x07170400,
570 0x00000000, 0xfff4cab4, 0x00087932, 0xfff1d4f2,
571 };
572
573 static const uint32_t vop_csc_y2r_bt601_12_235[] = {
574 0x000004a8, 0x04a80662, 0xfcbffe6f, 0x081204a8,
575 0x00000000, 0xfff2134e, 0x00087b58, 0xffeeb4b0,
576 };
577
578 static const uint32_t vop_csc_r2y_bt601[] = {
579 0x02590132, 0xff530075, 0x0200fead, 0xfe530200,
580 0x0000ffad, 0x00000200, 0x00080200, 0x00080200,
581 };
582
583 static const uint32_t vop_csc_r2y_bt601_12_235[] = {
584 0x02040107, 0xff680064, 0x01c2fed6, 0xfe8701c2,
585 0x0000ffb7, 0x00010200, 0x00080200, 0x00080200,
586 };
587
588 static const uint32_t vop_csc_y2r_bt709[] = {
589 0x000004a8, 0x04a8072c, 0xfddeff26, 0x087304a8,
590 0x00000000, 0xfff08077, 0x0004cfed, 0xffedf1b8,
591 };
592
593 static const uint32_t vop_csc_r2y_bt709[] = {
594 0x027500bb, 0xff99003f, 0x01c2fea5, 0xfe6801c2,
595 0x0000ffd7, 0x00010200, 0x00080200, 0x00080200,
596 };
597
598 static const uint32_t vop_csc_y2r_bt2020[] = {
599 0x000004a8, 0x04a806b6, 0xfd66ff40, 0x089004a8,
600 0x00000000, 0xfff16bfc, 0x00058ae9, 0xffedb828,
601 };
602
603 static const uint32_t vop_csc_r2y_bt2020[] = {
604 0x025300e6, 0xff830034, 0x01c1febd, 0xfe6401c1,
605 0x0000ffdc, 0x00010200, 0x00080200, 0x00080200,
606 };
607
608 static const uint32_t vop_csc_r2r_bt709_to_bt2020[] = {
609 0xfda606a4, 0xff80ffb5, 0xfff80488, 0xff99ffed,
610 0x0000047a, 0x00000200, 0x00000200, 0x00000200,
611 };
612
613 static const uint32_t vop_csc_r2r_bt2020_to_bt709[] = {
614 0x01510282, 0x0047002c, 0x000c03ae, 0x005a0011,
615 0x00000394, 0x00000200, 0x00000200, 0x00000200,
616 };
617
618 static const struct vop_csc_table rk3399_csc_table = {
619 .y2r_bt601 = vop_csc_y2r_bt601,
620 .y2r_bt601_12_235 = vop_csc_y2r_bt601_12_235,
621 .r2y_bt601 = vop_csc_r2y_bt601,
622 .r2y_bt601_12_235 = vop_csc_r2y_bt601_12_235,
623
624 .y2r_bt709 = vop_csc_y2r_bt709,
625 .r2y_bt709 = vop_csc_r2y_bt709,
626
627 .y2r_bt2020 = vop_csc_y2r_bt2020,
628 .r2y_bt2020 = vop_csc_r2y_bt2020,
629
630 .r2r_bt709_to_bt2020 = vop_csc_r2r_bt709_to_bt2020,
631 .r2r_bt2020_to_bt709 = vop_csc_r2r_bt2020_to_bt709,
632 };
633
634 static const struct vop_csc rk3399_win0_csc = {
635 .r2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 0),
636 .y2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 1),
637 .r2y_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 2),
638 .y2r_offset = RK3399_WIN0_YUV2YUV_Y2R,
639 .r2r_offset = RK3399_WIN0_YUV2YUV_3X3,
640 .r2y_offset = RK3399_WIN0_YUV2YUV_R2Y,
641 };
642
643 static const struct vop_csc rk3399_win1_csc = {
644 .r2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 8),
645 .y2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 9),
646 .r2y_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 10),
647 .y2r_offset = RK3399_WIN1_YUV2YUV_Y2R,
648 .r2r_offset = RK3399_WIN1_YUV2YUV_3X3,
649 .r2y_offset = RK3399_WIN1_YUV2YUV_R2Y,
650 };
651
652 static const struct vop_csc rk3399_win2_csc = {
653 .r2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 16),
654 .r2y_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 18),
655 .r2r_offset = RK3399_WIN2_YUV2YUV_3X3,
656 .csc_mode = VOP_REG(RK3399_YUV2YUV_WIN, 0x3, 22),
657 };
658
659 static const struct vop_csc rk3399_win3_csc = {
660 .r2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 24),
661 .r2y_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 26),
662 .r2r_offset = RK3399_WIN3_YUV2YUV_3X3,
663 .csc_mode = VOP_REG(RK3399_YUV2YUV_WIN, 0x3, 30),
664 };
665
666 static const struct vop_win_phy rk3399_win01_data = {
667 .scl = &rk3288_win_full_scl,
668 .data_formats = formats_win_full_10bit_yuyv,
669 .nformats = ARRAY_SIZE(formats_win_full_10bit_yuyv),
670 .enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
671 .format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
672 .fmt_10 = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 4),
673 .fmt_yuyv = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 17),
674 .csc_mode = VOP_REG_VER(RK3288_WIN0_CTRL0, 0x3, 10, 3, 2, -1),
675 .rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
676 .xmirror = VOP_REG_VER(RK3368_WIN0_CTRL0, 0x1, 21, 3, 2, -1),
677 .ymirror = VOP_REG_VER(RK3368_WIN0_CTRL0, 0x1, 22, 3, 2, -1),
678 .act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
679 .dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0),
680 .dsp_st = VOP_REG(RK3288_WIN0_DSP_ST, 0x1fff1fff, 0),
681 .yrgb_mst = VOP_REG(RK3288_WIN0_YRGB_MST, 0xffffffff, 0),
682 .uv_mst = VOP_REG(RK3288_WIN0_CBR_MST, 0xffffffff, 0),
683 .yrgb_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 0),
684 .uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16),
685 .src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xffff, 0),
686 .global_alpha_val = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xff, 16),
687 .dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xffffffff, 0),
688 .channel = VOP_REG_VER(RK3288_WIN0_CTRL2, 0xff, 0, 3, 8, 8),
689 .color_key = VOP_REG(RK3288_WIN0_COLOR_KEY, 0x3fffffff, 0),
690 .color_key_en = VOP_REG(RK3288_WIN0_COLOR_KEY, 0x1, 31),
691 };
692
693 static const struct vop_win_data rk3399_vop_win_data[] = {
694 { .base = 0x00, .phy = &rk3399_win01_data, .csc = &rk3399_win0_csc,
695 .format_modifiers = format_modifiers_afbc,
696 .type = DRM_PLANE_TYPE_PRIMARY,
697 .feature = WIN_FEATURE_AFBDC },
698 { .base = 0x40, .phy = &rk3399_win01_data, .csc = &rk3399_win1_csc,
699 .format_modifiers = format_modifiers_afbc,
700 .type = DRM_PLANE_TYPE_OVERLAY,
701 .feature = WIN_FEATURE_AFBDC },
702 { .base = 0x00, .phy = &rk3368_win23_data, .csc = &rk3399_win2_csc,
703 .format_modifiers = format_modifiers_afbc,
704 .type = DRM_PLANE_TYPE_OVERLAY,
705 .feature = WIN_FEATURE_AFBDC,
706 .area = rk3368_area_data,
707 .area_size = ARRAY_SIZE(rk3368_area_data), },
708 { .base = 0x50, .phy = &rk3368_win23_data, .csc = &rk3399_win3_csc,
709 .format_modifiers = format_modifiers_afbc,
710 .type = DRM_PLANE_TYPE_CURSOR,
711 .feature = WIN_FEATURE_AFBDC,
712 .area = rk3368_area_data,
713 .area_size = ARRAY_SIZE(rk3368_area_data), },
714 };
715
716 static const struct vop_data rk3399_vop_big = {
717 .soc_id = 0x3399,
718 .vop_id = 0,
719 .version = VOP_VERSION(3, 5),
720 .csc_table = &rk3399_csc_table,
721 .feature = VOP_FEATURE_OUTPUT_10BIT | VOP_FEATURE_ALPHA_SCALE | VOP_FEATURE_OVERSCAN,
722 .max_input = {4096, 8192},
723 .max_output = {4096, 2160},
724 .intr = &rk3366_vop_intr,
725 .ctrl = &rk3288_ctrl_data,
726 .win = rk3399_vop_win_data,
727 .win_size = ARRAY_SIZE(rk3399_vop_win_data),
728 };
729
730 static const struct vop_win_data rk3399_vop_lit_win_data[] = {
731 { .base = 0x00, .phy = &rk3399_win01_data, .csc = &rk3399_win0_csc,
732 .format_modifiers = format_modifiers,
733 .type = DRM_PLANE_TYPE_OVERLAY,
734 .feature = WIN_FEATURE_AFBDC },
735 { .phy = NULL },
736 { .base = 0x00, .phy = &rk3368_win23_data, .csc = &rk3399_win2_csc,
737 .format_modifiers = format_modifiers,
738 .type = DRM_PLANE_TYPE_PRIMARY,
739 .feature = WIN_FEATURE_AFBDC,
740 .area = rk3368_area_data,
741 .area_size = ARRAY_SIZE(rk3368_area_data), },
742 { .phy = NULL },
743 };
744
745
746 static const struct vop_data rk3399_vop_lit = {
747 .soc_id = 0x3399,
748 .vop_id = 1,
749 .version = VOP_VERSION(3, 6),
750 .feature = VOP_FEATURE_ALPHA_SCALE | VOP_FEATURE_OVERSCAN,
751 .csc_table = &rk3399_csc_table,
752 .max_input = {4096, 8192},
753 .max_output = {2560, 1600},
754 .intr = &rk3366_vop_intr,
755 .ctrl = &rk3288_ctrl_data,
756 .win = rk3399_vop_lit_win_data,
757 .win_size = ARRAY_SIZE(rk3399_vop_lit_win_data),
758 };
759
760 static const struct vop_win_data rk322x_vop_win_data[] = {
761 { .base = 0x00, .phy = &rk3288_win01_data,
762 .type = DRM_PLANE_TYPE_PRIMARY },
763 { .base = 0x40, .phy = &rk3288_win01_data,
764 .type = DRM_PLANE_TYPE_CURSOR },
765 };
766
767 static const struct vop_data rk3228_vop = {
768 .soc_id = 0x3228,
769 .vop_id = 0,
770 .version = VOP_VERSION(3, 7),
771 .feature = VOP_FEATURE_OUTPUT_10BIT | VOP_FEATURE_ALPHA_SCALE | VOP_FEATURE_OVERSCAN,
772 .max_input = {4096, 8192},
773 .max_output = {4096, 2160},
774 .intr = &rk3366_vop_intr,
775 .ctrl = &rk3288_ctrl_data,
776 .win = rk322x_vop_win_data,
777 .win_size = ARRAY_SIZE(rk322x_vop_win_data),
778 };
779
780 static const u32 sdr2hdr_bt1886eotf_yn_for_hlg_hdr[65] = {
781 0,
782 1, 7, 17, 35,
783 60, 92, 134, 184,
784 244, 315, 396, 487,
785 591, 706, 833, 915,
786 1129, 1392, 1717, 2118,
787 2352, 2612, 2900, 3221,
788 3577, 3972, 4411, 4899,
789 5441, 6042, 6710, 7452,
790 7853, 8276, 8721, 9191,
791 9685, 10207, 10756, 11335,
792 11945, 12588, 13266, 13980,
793 14732, 15525, 16361, 17241,
794 17699, 18169, 18652, 19147,
795 19656, 20178, 20714, 21264,
796 21829, 22408, 23004, 23615,
797 24242, 24886, 25547, 26214,
798 };
799
800 static const u32 sdr2hdr_bt1886eotf_yn_for_bt2020[65] = {
801 0,
802 1820, 3640, 5498, 7674,
803 10256, 13253, 16678, 20539,
804 24847, 29609, 34833, 40527,
805 46699, 53354, 60499, 68141,
806 76285, 84937, 94103, 103787,
807 108825, 113995, 119296, 124731,
808 130299, 136001, 141837, 147808,
809 153915, 160158, 166538, 173055,
810 176365, 179709, 183089, 186502,
811 189951, 193434, 196952, 200505,
812 204093, 207715, 211373, 215066,
813 218795, 222558, 226357, 230191,
814 232121, 234060, 236008, 237965,
815 239931, 241906, 243889, 245882,
816 247883, 249894, 251913, 253941,
817 255978, 258024, 260079, 262143,
818 };
819
820 static u32 sdr2hdr_bt1886eotf_yn_for_hdr[65] = {
821 /* dst_range 425int */
822 0,
823 5, 21, 49, 91,
824 150, 225, 320, 434,
825 569, 726, 905, 1108,
826 1336, 1588, 1866, 2171,
827 2502, 2862, 3250, 3667,
828 3887, 4114, 4349, 4591,
829 4841, 5099, 5364, 5638,
830 5920, 6209, 6507, 6812,
831 6968, 7126, 7287, 7449,
832 7613, 7779, 7948, 8118,
833 8291, 8466, 8643, 8822,
834 9003, 9187, 9372, 9560,
835 9655, 9750, 9846, 9942,
836 10039, 10136, 10234, 10333,
837 10432, 10531, 10631, 10732,
838 10833, 10935, 11038, 11141,
839 };
840
841 static const u32 sdr2hdr_st2084oetf_yn_for_hlg_hdr[65] = {
842 0,
843 668, 910, 1217, 1600,
844 2068, 2384, 2627, 3282,
845 3710, 4033, 4879, 5416,
846 5815, 6135, 6401, 6631,
847 6833, 7176, 7462, 7707,
848 7921, 8113, 8285, 8442,
849 8586, 8843, 9068, 9268,
850 9447, 9760, 10027, 10259,
851 10465, 10650, 10817, 10971,
852 11243, 11480, 11689, 11877,
853 12047, 12202, 12345, 12477,
854 12601, 12716, 12926, 13115,
855 13285, 13441, 13583, 13716,
856 13839, 13953, 14163, 14350,
857 14519, 14673, 14945, 15180,
858 15570, 15887, 16153, 16383,
859 };
860
861 static const u32 sdr2hdr_st2084oetf_yn_for_bt2020[65] = {
862 0,
863 0, 0, 1, 2,
864 4, 6, 9, 18,
865 27, 36, 72, 108,
866 144, 180, 216, 252,
867 288, 360, 432, 504,
868 576, 648, 720, 792,
869 864, 1008, 1152, 1296,
870 1444, 1706, 1945, 2166,
871 2372, 2566, 2750, 2924,
872 3251, 3553, 3834, 4099,
873 4350, 4588, 4816, 5035,
874 5245, 5447, 5832, 6194,
875 6536, 6862, 7173, 7471,
876 7758, 8035, 8560, 9055,
877 9523, 9968, 10800, 11569,
878 12963, 14210, 15347, 16383,
879 };
880
881 static u32 sdr2hdr_st2084oetf_yn_for_hdr[65] = {
882 0,
883 281, 418, 610, 871,
884 1217, 1464, 1662, 2218,
885 2599, 2896, 3699, 4228,
886 4628, 4953, 5227, 5466,
887 5676, 6038, 6341, 6602,
888 6833, 7039, 7226, 7396,
889 7554, 7835, 8082, 8302,
890 8501, 8848, 9145, 9405,
891 9635, 9842, 10031, 10204,
892 10512, 10779, 11017, 11230,
893 11423, 11599, 11762, 11913,
894 12054, 12185, 12426, 12641,
895 12835, 13013, 13177, 13328,
896 13469, 13600, 13840, 14055,
897 14248, 14425, 14737, 15006,
898 15453, 15816, 16121, 16383,
899 };
900
901 static const u32 sdr2hdr_st2084oetf_dxn_pow2[64] = {
902 0, 0, 1, 2,
903 3, 3, 3, 5,
904 5, 5, 7, 7,
905 7, 7, 7, 7,
906 7, 8, 8, 8,
907 8, 8, 8, 8,
908 8, 9, 9, 9,
909 9, 10, 10, 10,
910 10, 10, 10, 10,
911 11, 11, 11, 11,
912 11, 11, 11, 11,
913 11, 11, 12, 12,
914 12, 12, 12, 12,
915 12, 12, 13, 13,
916 13, 13, 14, 14,
917 15, 15, 15, 15,
918 };
919
920 static const u32 sdr2hdr_st2084oetf_dxn[64] = {
921 1, 1, 2, 4,
922 8, 8, 8, 32,
923 32, 32, 128, 128,
924 128, 128, 128, 128,
925 128, 256, 256, 256,
926 256, 256, 256, 256,
927 256, 512, 512, 512,
928 512, 1024, 1024, 1024,
929 1024, 1024, 1024, 1024,
930 2048, 2048, 2048, 2048,
931 2048, 2048, 2048, 2048,
932 2048, 2048, 4096, 4096,
933 4096, 4096, 4096, 4096,
934 4096, 4096, 8192, 8192,
935 8192, 8192, 16384, 16384,
936 32768, 32768, 32768, 32768,
937 };
938
939 static const u32 sdr2hdr_st2084oetf_xn[63] = {
940 1, 2, 4, 8,
941 16, 24, 32, 64,
942 96, 128, 256, 384,
943 512, 640, 768, 896,
944 1024, 1280, 1536, 1792,
945 2048, 2304, 2560, 2816,
946 3072, 3584, 4096, 4608,
947 5120, 6144, 7168, 8192,
948 9216, 10240, 11264, 12288,
949 14336, 16384, 18432, 20480,
950 22528, 24576, 26624, 28672,
951 30720, 32768, 36864, 40960,
952 45056, 49152, 53248, 57344,
953 61440, 65536, 73728, 81920,
954 90112, 98304, 114688, 131072,
955 163840, 196608, 229376,
956 };
957
958 static u32 hdr2sdr_eetf_yn[33] = {
959 1716,
960 1880, 2067, 2277, 2508,
961 2758, 3026, 3310, 3609,
962 3921, 4246, 4581, 4925,
963 5279, 5640, 6007, 6380,
964 6758, 7140, 7526, 7914,
965 8304, 8694, 9074, 9438,
966 9779, 10093, 10373, 10615,
967 10812, 10960, 11053, 11084,
968 };
969
970 static u32 hdr2sdr_bt1886oetf_yn[33] = {
971 0,
972 0, 0, 0, 0,
973 0, 0, 0, 314,
974 746, 1323, 2093, 2657,
975 3120, 3519, 3874, 4196,
976 4492, 5024, 5498, 5928,
977 6323, 7034, 7666, 8239,
978 8766, 9716, 10560, 11325,
979 12029, 13296, 14422, 16383,
980 };
981
982 static const u32 hdr2sdr_sat_yn[9] = {
983 0,
984 1792, 3584, 3472, 2778,
985 2083, 1389, 694, 0,
986 };
987
988 static const struct vop_hdr_table rk3328_hdr_table = {
989 .hdr2sdr_eetf_oetf_y0_offset = RK3328_HDR2SDR_EETF_OETF_Y0,
990 .hdr2sdr_eetf_oetf_y1_offset = RK3328_HDR2SDR_EETF_OETF_Y1,
991 .hdr2sdr_eetf_yn = hdr2sdr_eetf_yn,
992 .hdr2sdr_bt1886oetf_yn = hdr2sdr_bt1886oetf_yn,
993 .hdr2sdr_sat_y0_offset = RK3328_HDR2DR_SAT_Y0,
994 .hdr2sdr_sat_y1_offset = RK3328_HDR2DR_SAT_Y1,
995 .hdr2sdr_sat_yn = hdr2sdr_sat_yn,
996
997 .hdr2sdr_src_range_min = 494,
998 .hdr2sdr_src_range_max = 12642,
999 .hdr2sdr_normfaceetf = 1327,
1000 .hdr2sdr_dst_range_min = 4,
1001 .hdr2sdr_dst_range_max = 3276,
1002 .hdr2sdr_normfacgamma = 5120,
1003
1004 .sdr2hdr_eotf_oetf_y0_offset = RK3328_SDR2HDR_EOTF_OETF_Y0,
1005 .sdr2hdr_eotf_oetf_y1_offset = RK3328_SDR2HDR_EOTF_OETF_Y1,
1006 .sdr2hdr_bt1886eotf_yn_for_hlg_hdr = sdr2hdr_bt1886eotf_yn_for_hlg_hdr,
1007 .sdr2hdr_bt1886eotf_yn_for_bt2020 = sdr2hdr_bt1886eotf_yn_for_bt2020,
1008 .sdr2hdr_bt1886eotf_yn_for_hdr = sdr2hdr_bt1886eotf_yn_for_hdr,
1009 .sdr2hdr_st2084oetf_yn_for_hlg_hdr = sdr2hdr_st2084oetf_yn_for_hlg_hdr,
1010 .sdr2hdr_st2084oetf_yn_for_bt2020 = sdr2hdr_st2084oetf_yn_for_bt2020,
1011 .sdr2hdr_st2084oetf_yn_for_hdr = sdr2hdr_st2084oetf_yn_for_hdr,
1012 .sdr2hdr_oetf_dx_dxpow1_offset = RK3328_SDR2HDR_OETF_DX_DXPOW1,
1013 .sdr2hdr_oetf_xn1_offset = RK3328_SDR2HDR_OETF_XN1,
1014 .sdr2hdr_st2084oetf_dxn_pow2 = sdr2hdr_st2084oetf_dxn_pow2,
1015 .sdr2hdr_st2084oetf_dxn = sdr2hdr_st2084oetf_dxn,
1016 .sdr2hdr_st2084oetf_xn = sdr2hdr_st2084oetf_xn,
1017 };
1018
1019 static const struct vop_ctrl rk3328_ctrl_data = {
1020 .standby = VOP_REG(RK3328_SYS_CTRL, 0x1, 22),
1021 .dma_stop = VOP_REG(RK3328_SYS_CTRL, 0x1, 21),
1022 .axi_outstanding_max_num = VOP_REG(RK3328_SYS_CTRL1, 0x1f, 13),
1023 .axi_max_outstanding_en = VOP_REG(RK3328_SYS_CTRL1, 0x1, 12),
1024 .reg_done_frm = VOP_REG(RK3328_SYS_CTRL1, 0x1, 24),
1025 .auto_gate_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 23),
1026 .htotal_pw = VOP_REG(RK3328_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
1027 .hact_st_end = VOP_REG(RK3328_DSP_HACT_ST_END, 0x1fff1fff, 0),
1028 .vtotal_pw = VOP_REG(RK3328_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
1029 .vact_st_end = VOP_REG(RK3328_DSP_VACT_ST_END, 0x1fff1fff, 0),
1030 .vact_st_end_f1 = VOP_REG(RK3328_DSP_VACT_ST_END_F1, 0x1fff1fff, 0),
1031 .vs_st_end_f1 = VOP_REG(RK3328_DSP_VS_ST_END_F1, 0x1fff1fff, 0),
1032 .hpost_st_end = VOP_REG(RK3328_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
1033 .vpost_st_end = VOP_REG(RK3328_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
1034 .vpost_st_end_f1 = VOP_REG(RK3328_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0),
1035 .post_scl_factor = VOP_REG(RK3328_POST_SCL_FACTOR_YRGB, 0xffffffff, 0),
1036 .post_scl_ctrl = VOP_REG(RK3328_POST_SCL_CTRL, 0x3, 0),
1037 .dsp_out_yuv = VOP_REG(RK3328_POST_SCL_CTRL, 0x1, 2),
1038 .dsp_interlace = VOP_REG(RK3328_DSP_CTRL0, 0x1, 10),
1039 .dsp_layer_sel = VOP_REG(RK3328_DSP_CTRL1, 0xff, 8),
1040 .post_lb_mode = VOP_REG(RK3328_SYS_CTRL, 0x1, 18),
1041 .global_regdone_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 11),
1042 .overlay_mode = VOP_REG(RK3328_SYS_CTRL, 0x1, 16),
1043 .core_dclk_div = VOP_REG(RK3328_DSP_CTRL0, 0x1, 4),
1044 .dclk_ddr = VOP_REG(RK3328_DSP_CTRL0, 0x1, 8),
1045 .p2i_en = VOP_REG(RK3328_DSP_CTRL0, 0x1, 5),
1046 .rgb_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 12),
1047 .hdmi_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 13),
1048 .edp_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 14),
1049 .mipi_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 15),
1050 .tve_dclk_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 24),
1051 .tve_dclk_pol = VOP_REG(RK3328_SYS_CTRL, 0x1, 25),
1052 .tve_sw_mode = VOP_REG(RK3328_SYS_CTRL, 0x1, 26),
1053 .sw_uv_offset_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 27),
1054 .sw_genlock = VOP_REG(RK3328_SYS_CTRL, 0x1, 28),
1055 .sw_dac_sel = VOP_REG(RK3328_SYS_CTRL, 0x1, 29),
1056 .rgb_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0x7, 16),
1057 .hdmi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0x7, 20),
1058 .edp_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0x7, 24),
1059 .mipi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0x7, 28),
1060 .rgb_dclk_pol = VOP_REG(RK3328_DSP_CTRL1, 0x1, 19),
1061 .hdmi_dclk_pol = VOP_REG(RK3328_DSP_CTRL1, 0x1, 23),
1062 .edp_dclk_pol = VOP_REG(RK3328_DSP_CTRL1, 0x1, 27),
1063 .mipi_dclk_pol = VOP_REG(RK3328_DSP_CTRL1, 0x1, 31),
1064
1065 .dither_down_sel = VOP_REG(RK3328_DSP_CTRL1, 0x1, 4),
1066 .dither_down_mode = VOP_REG(RK3328_DSP_CTRL1, 0x1, 3),
1067 .dither_down_en = VOP_REG(RK3328_DSP_CTRL1, 0x1, 2),
1068 .pre_dither_down_en = VOP_REG(RK3328_DSP_CTRL1, 0x1, 1),
1069 .dither_up_en = VOP_REG(RK3328_DSP_CTRL1, 0x1, 6),
1070
1071 .dsp_data_swap = VOP_REG(RK3328_DSP_CTRL0, 0x1f, 12),
1072 .dsp_bg_swap = VOP_REG(RK3328_DSP_CTRL0, 0x1, 12),
1073 .dsp_rb_swap = VOP_REG(RK3328_DSP_CTRL0, 0x1, 13),
1074 .dsp_rg_swap = VOP_REG(RK3328_DSP_CTRL0, 0x1, 14),
1075 .dsp_delta_swap = VOP_REG(RK3328_DSP_CTRL0, 0x1, 15),
1076 .dsp_dummy_swap = VOP_REG(RK3328_DSP_CTRL0, 0x1, 16),
1077 .dsp_ccir656_avg = VOP_REG(RK3328_DSP_CTRL0, 0x1, 20),
1078 .dsp_blank = VOP_REG(RK3328_DSP_CTRL0, 0x3, 18),
1079 .dsp_lut_en = VOP_REG(RK3328_DSP_CTRL1, 0x1, 0),
1080 .out_mode = VOP_REG(RK3328_DSP_CTRL0, 0xf, 0),
1081
1082 .xmirror = VOP_REG(RK3328_DSP_CTRL0, 0x1, 22),
1083 .ymirror = VOP_REG(RK3328_DSP_CTRL0, 0x1, 23),
1084
1085 .dsp_background = VOP_REG(RK3328_DSP_BG, 0xffffffff, 0),
1086
1087 .alpha_hard_calc = VOP_REG(RK3328_SYS_CTRL1, 0x1, 27),
1088 .level2_overlay_en = VOP_REG(RK3328_SYS_CTRL1, 0x1, 28),
1089
1090 .hdr2sdr_en = VOP_REG(RK3328_HDR2DR_CTRL, 0x1, 0),
1091 .hdr2sdr_en_win0_csc = VOP_REG(RK3328_SDR2HDR_CTRL, 0x1, 9),
1092 .hdr2sdr_src_min = VOP_REG(RK3328_HDR2DR_SRC_RANGE, 0x3fff, 0),
1093 .hdr2sdr_src_max = VOP_REG(RK3328_HDR2DR_SRC_RANGE, 0x3fff, 16),
1094 .hdr2sdr_normfaceetf = VOP_REG(RK3328_HDR2DR_NORMFACEETF, 0x7ff, 0),
1095 .hdr2sdr_dst_min = VOP_REG(RK3328_HDR2DR_DST_RANGE, 0x3fff, 0),
1096 .hdr2sdr_dst_max = VOP_REG(RK3328_HDR2DR_DST_RANGE, 0x3fff, 16),
1097 .hdr2sdr_normfacgamma = VOP_REG(RK3328_HDR2DR_NORMFACGAMMA, 0xffff, 0),
1098
1099 .bt1886eotf_pre_conv_en = VOP_REG(RK3328_SDR2HDR_CTRL, 0x1, 0),
1100 .rgb2rgb_pre_conv_en = VOP_REG(RK3328_SDR2HDR_CTRL, 0x1, 1),
1101 .rgb2rgb_pre_conv_mode = VOP_REG(RK3328_SDR2HDR_CTRL, 0x1, 2),
1102 .st2084oetf_pre_conv_en = VOP_REG(RK3328_SDR2HDR_CTRL, 0x1, 3),
1103 .bt1886eotf_post_conv_en = VOP_REG(RK3328_SDR2HDR_CTRL, 0x1, 4),
1104 .rgb2rgb_post_conv_en = VOP_REG(RK3328_SDR2HDR_CTRL, 0x1, 5),
1105 .rgb2rgb_post_conv_mode = VOP_REG(RK3328_SDR2HDR_CTRL, 0x1, 6),
1106 .st2084oetf_post_conv_en = VOP_REG(RK3328_SDR2HDR_CTRL, 0x1, 7),
1107 .win_csc_mode_sel = VOP_REG(RK3328_SDR2HDR_CTRL, 0x1, 31),
1108
1109 .bcsh_brightness = VOP_REG(RK3328_BCSH_BCS, 0xff, 0),
1110 .bcsh_contrast = VOP_REG(RK3328_BCSH_BCS, 0x1ff, 8),
1111 .bcsh_sat_con = VOP_REG(RK3328_BCSH_BCS, 0x3ff, 20),
1112 .bcsh_out_mode = VOP_REG(RK3328_BCSH_BCS, 0x3, 30),
1113 .bcsh_sin_hue = VOP_REG(RK3328_BCSH_H, 0x1ff, 0),
1114 .bcsh_cos_hue = VOP_REG(RK3328_BCSH_H, 0x1ff, 16),
1115 .bcsh_r2y_csc_mode = VOP_REG(RK3328_BCSH_CTRL, 0x3, 6),
1116 .bcsh_r2y_en = VOP_REG(RK3328_BCSH_CTRL, 0x1, 4),
1117 .bcsh_y2r_csc_mode = VOP_REG(RK3328_BCSH_CTRL, 0x3, 2),
1118 .bcsh_y2r_en = VOP_REG(RK3328_BCSH_CTRL, 0x1, 0),
1119 .bcsh_color_bar = VOP_REG(RK3328_BCSH_COLOR_BAR, 0xffffff, 8),
1120 .bcsh_en = VOP_REG(RK3328_BCSH_COLOR_BAR, 0x1, 0),
1121
1122 .cfg_done = VOP_REG(RK3328_REG_CFG_DONE, 0x1, 0),
1123 };
1124
1125 static const struct vop_intr rk3328_vop_intr = {
1126 .intrs = rk3368_vop_intrs,
1127 .nintrs = ARRAY_SIZE(rk3368_vop_intrs),
1128 .line_flag_num[0] = VOP_REG(RK3328_LINE_FLAG, 0xffff, 0),
1129 .line_flag_num[1] = VOP_REG(RK3328_LINE_FLAG, 0xffff, 16),
1130 .status = VOP_REG_MASK(RK3328_INTR_STATUS0, 0xffff, 0),
1131 .enable = VOP_REG_MASK(RK3328_INTR_EN0, 0xffff, 0),
1132 .clear = VOP_REG_MASK(RK3328_INTR_CLEAR0, 0xffff, 0),
1133 };
1134
1135 static const struct vop_csc rk3328_win0_csc = {
1136 .r2y_en = VOP_REG(RK3328_SDR2HDR_CTRL, 0x1, 8),
1137 .r2r_en = VOP_REG(RK3328_SDR2HDR_CTRL, 0x1, 5),
1138 .y2r_en = VOP_REG(RK3328_SDR2HDR_CTRL, 0x1, 9),
1139 };
1140
1141 static const struct vop_csc rk3328_win1_csc = {
1142 .r2y_en = VOP_REG(RK3328_SDR2HDR_CTRL, 0x1, 10),
1143 .r2r_en = VOP_REG(RK3328_SDR2HDR_CTRL, 0x1, 1),
1144 .y2r_en = VOP_REG(RK3328_SDR2HDR_CTRL, 0x1, 11),
1145 };
1146
1147 static const struct vop_csc rk3328_win2_csc = {
1148 .r2y_en = VOP_REG(RK3328_SDR2HDR_CTRL, 0x1, 12),
1149 .r2r_en = VOP_REG(RK3328_SDR2HDR_CTRL, 0x1, 1),
1150 .y2r_en = VOP_REG(RK3328_SDR2HDR_CTRL, 0x1, 13),
1151 };
1152
1153 static const struct vop_win_data rk3328_vop_win_data[] = {
1154 { .base = 0xd0, .phy = &rk3288_win01_data, .csc = &rk3328_win0_csc,
1155 .type = DRM_PLANE_TYPE_PRIMARY,
1156 .feature = WIN_FEATURE_HDR2SDR | WIN_FEATURE_SDR2HDR },
1157 { .base = 0x1d0, .phy = &rk3288_win01_data, .csc = &rk3328_win1_csc,
1158 .type = DRM_PLANE_TYPE_OVERLAY,
1159 .feature = WIN_FEATURE_SDR2HDR | WIN_FEATURE_PRE_OVERLAY },
1160 { .base = 0x2d0, .phy = &rk3288_win01_data, .csc = &rk3328_win2_csc,
1161 .type = DRM_PLANE_TYPE_CURSOR,
1162 .feature = WIN_FEATURE_SDR2HDR | WIN_FEATURE_PRE_OVERLAY },
1163 };
1164
1165 static const struct vop_data rk3328_vop = {
1166 .soc_id = 0x3328,
1167 .vop_id = 0,
1168 .version = VOP_VERSION(3, 8),
1169 .feature = VOP_FEATURE_OUTPUT_10BIT | VOP_FEATURE_HDR10 |
1170 VOP_FEATURE_ALPHA_SCALE | VOP_FEATURE_OVERSCAN,
1171 .hdr_table = &rk3328_hdr_table,
1172 .max_input = {4096, 8192},
1173 .max_output = {4096, 2160},
1174 .intr = &rk3328_vop_intr,
1175 .ctrl = &rk3328_ctrl_data,
1176 .win = rk3328_vop_win_data,
1177 .win_size = ARRAY_SIZE(rk3328_vop_win_data),
1178 };
1179
1180 static const struct vop_scl_regs rk3036_win0_scl = {
1181 .scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
1182 .scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
1183 .scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
1184 .scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
1185 };
1186
1187 static const struct vop_scl_regs rk3036_win1_scl = {
1188 .scale_yrgb_x = VOP_REG(RK3036_WIN1_SCL_FACTOR_YRGB, 0xffff, 0x0),
1189 .scale_yrgb_y = VOP_REG(RK3036_WIN1_SCL_FACTOR_YRGB, 0xffff, 16),
1190 };
1191
1192 static const struct vop_win_phy rk3036_win0_data = {
1193 .scl = &rk3036_win0_scl,
1194 .data_formats = formats_win_full,
1195 .nformats = ARRAY_SIZE(formats_win_full),
1196 .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0),
1197 .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3),
1198 .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15),
1199 .act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0),
1200 .dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0),
1201 .dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0),
1202 .yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0),
1203 .uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0),
1204 .yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0),
1205 .uv_vir = VOP_REG(RK3036_WIN0_VIR, 0x1fff, 16),
1206 .alpha_mode = VOP_REG(RK3036_DSP_CTRL0, 0x1, 18),
1207 .alpha_en = VOP_REG(RK3036_ALPHA_CTRL, 0x1, 0),
1208 .alpha_pre_mul = VOP_REG(RK3036_DSP_CTRL0, 0x1, 29),
1209 };
1210
1211 static const struct vop_win_phy rk3036_win1_data = {
1212 .scl = &rk3036_win1_scl,
1213 .data_formats = formats_win_lite,
1214 .nformats = ARRAY_SIZE(formats_win_lite),
1215 .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1),
1216 .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6),
1217 .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19),
1218 .act_info = VOP_REG(RK3036_WIN1_ACT_INFO, 0x1fff1fff, 0),
1219 .dsp_info = VOP_REG(RK3036_WIN1_DSP_INFO, 0x0fff0fff, 0),
1220 .dsp_st = VOP_REG(RK3036_WIN1_DSP_ST, 0x1fff1fff, 0),
1221 .yrgb_mst = VOP_REG(RK3036_WIN1_MST, 0xffffffff, 0),
1222 .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0),
1223 .alpha_mode = VOP_REG(RK3036_DSP_CTRL0, 0x1, 19),
1224 .alpha_en = VOP_REG(RK3036_ALPHA_CTRL, 0x1, 1)
1225 };
1226
1227 static const struct vop_win_data rk3036_vop_win_data[] = {
1228 { .base = 0x00, .phy = &rk3036_win0_data,
1229 .type = DRM_PLANE_TYPE_PRIMARY },
1230 { .base = 0x00, .phy = &rk3036_win1_data,
1231 .type = DRM_PLANE_TYPE_OVERLAY },
1232 };
1233
1234 static const int rk3036_vop_intrs[] = {
1235 DSP_HOLD_VALID_INTR,
1236 FS_INTR,
1237 LINE_FLAG_INTR,
1238 BUS_ERROR_INTR,
1239 };
1240
1241 static const struct vop_intr rk3036_intr = {
1242 .intrs = rk3036_vop_intrs,
1243 .nintrs = ARRAY_SIZE(rk3036_vop_intrs),
1244 .line_flag_num[0] = VOP_REG(RK3036_INT_STATUS, 0xfff, 12),
1245 .status = VOP_REG(RK3036_INT_STATUS, 0xf, 0),
1246 .enable = VOP_REG(RK3036_INT_STATUS, 0xf, 4),
1247 .clear = VOP_REG(RK3036_INT_STATUS, 0xf, 8),
1248 };
1249
1250 static const struct vop_ctrl rk3036_ctrl_data = {
1251 .standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30),
1252 .sw_dac_sel = VOP_REG(RK3036_SYS_CTRL, 0x1, 29),
1253 .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0),
1254 .dsp_interlace = VOP_REG(RK3036_DSP_CTRL0, 0x1, 12),
1255 .dsp_blank = VOP_REG(RK3036_DSP_CTRL1, 0x1, 24),
1256 .dsp_background = VOP_REG(RK3036_DSP_CTRL1, 0xffffff, 0),
1257 .dclk_pol = VOP_REG(RK3036_DSP_CTRL0, 0x1, 7),
1258 .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0x7, 4),
1259 .dither_down_sel = VOP_REG(RK3036_DSP_CTRL0, 0x1, 27),
1260 .tve_sw_mode = VOP_REG(RK3036_DSP_CTRL0, 0x1, 25),
1261 .dsp_interlace_pol = VOP_REG(RK3036_DSP_CTRL0, 0x1, 13),
1262 .dither_down_en = VOP_REG(RK3036_DSP_CTRL0, 0x1, 11),
1263 .dither_down_mode = VOP_REG(RK3036_DSP_CTRL0, 0x1, 10),
1264 .dither_up_en = VOP_REG(RK3036_DSP_CTRL0, 0x1, 9),
1265 .dsp_layer_sel = VOP_REG(RK3036_DSP_CTRL0, 0x1, 8),
1266 .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
1267 .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0),
1268 .tve_dclk_en = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 20),
1269 .tve_dclk_pol = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 21),
1270 .hdmi_en = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 22),
1271 .hdmi_dclk_pol = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 23),
1272 .core_dclk_div = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 30),
1273 .hdmi_pin_pol = VOP_REG(RK3036_INT_SCALER, 0x7, 4),
1274 .rgb_en = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 24),
1275 .rgb_dclk_pol = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 25),
1276 .lvds_en = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 26),
1277 .lvds_dclk_pol = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 27),
1278 .mipi_en = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 28),
1279 .mipi_dclk_pol = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 29),
1280 .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
1281 .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0),
1282 .vs_st_end_f1 = VOP_REG(RK3036_DSP_VS_ST_END_F1, 0x1fff1fff, 0),
1283 .vact_st_end_f1 = VOP_REG(RK3036_DSP_VACT_ST_END_F1, 0x1fff1fff, 0),
1284 .cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0),
1285 };
1286
1287 static const struct vop_data rk3036_vop = {
1288 .soc_id = 0x3036,
1289 .vop_id = 0,
1290 .version = VOP_VERSION(2, 2),
1291 .max_input = {1920, 1080},
1292 .max_output = {1920, 1080},
1293 .ctrl = &rk3036_ctrl_data,
1294 .intr = &rk3036_intr,
1295 .win = rk3036_vop_win_data,
1296 .win_size = ARRAY_SIZE(rk3036_vop_win_data),
1297 };
1298
1299 static const struct vop_scl_regs rk3066_win_scl = {
1300 .scale_yrgb_x = VOP_REG(RK3066_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
1301 .scale_yrgb_y = VOP_REG(RK3066_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
1302 .scale_cbcr_x = VOP_REG(RK3066_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
1303 .scale_cbcr_y = VOP_REG(RK3066_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
1304 };
1305
1306 static const struct vop_win_phy rk3066_win0_data = {
1307 .scl = &rk3066_win_scl,
1308 .data_formats = formats_win_full,
1309 .nformats = ARRAY_SIZE(formats_win_full),
1310 .enable = VOP_REG(RK3066_SYS_CTRL1, 0x1, 0),
1311 .format = VOP_REG(RK3066_SYS_CTRL0, 0x7, 4),
1312 .rb_swap = VOP_REG(RK3066_SYS_CTRL0, 0x1, 19),
1313 .act_info = VOP_REG(RK3066_WIN0_ACT_INFO, 0x1fff1fff, 0),
1314 .dsp_info = VOP_REG(RK3066_WIN0_DSP_INFO, 0x0fff0fff, 0),
1315 .dsp_st = VOP_REG(RK3066_WIN0_DSP_ST, 0x1fff1fff, 0),
1316 .yrgb_mst = VOP_REG(RK3066_WIN0_YRGB_MST0, 0xffffffff, 0),
1317 .uv_mst = VOP_REG(RK3066_WIN0_CBR_MST0, 0xffffffff, 0),
1318 .yrgb_vir = VOP_REG(RK3066_WIN0_VIR, 0xffff, 0),
1319 .uv_vir = VOP_REG(RK3066_WIN0_VIR, 0x1fff, 16),
1320 .alpha_mode = VOP_REG(RK3066_DSP_CTRL0, 0x1, 21),
1321 .alpha_en = VOP_REG(RK3066_BLEND_CTRL, 0x1, 0)
1322 };
1323
1324 static const struct vop_win_phy rk3066_win1_data = {
1325 .scl = &rk3066_win_scl,
1326 .data_formats = formats_win_full,
1327 .nformats = ARRAY_SIZE(formats_win_full),
1328 .enable = VOP_REG(RK3066_SYS_CTRL1, 0x1, 1),
1329 .format = VOP_REG(RK3066_SYS_CTRL0, 0x7, 7),
1330 .rb_swap = VOP_REG(RK3066_SYS_CTRL0, 0x1, 23),
1331 .act_info = VOP_REG(RK3066_WIN1_ACT_INFO, 0x1fff1fff, 0),
1332 .dsp_info = VOP_REG(RK3066_WIN1_DSP_INFO, 0x0fff0fff, 0),
1333 .dsp_st = VOP_REG(RK3066_WIN1_DSP_ST, 0x1fff1fff, 0),
1334 .yrgb_mst = VOP_REG(RK3066_WIN1_YRGB_MST, 0xffffffff, 0),
1335 .uv_mst = VOP_REG(RK3066_WIN1_CBR_MST, 0xffffffff, 0),
1336 .yrgb_vir = VOP_REG(RK3066_WIN1_VIR, 0xffff, 0),
1337 .uv_vir = VOP_REG(RK3066_WIN1_VIR, 0x1fff, 16),
1338 .alpha_mode = VOP_REG(RK3066_DSP_CTRL0, 0x1, 22),
1339 .alpha_en = VOP_REG(RK3066_BLEND_CTRL, 0x1, 1)
1340 };
1341
1342 static const struct vop_win_phy rk3066_win2_data = {
1343 .data_formats = formats_win_lite,
1344 .nformats = ARRAY_SIZE(formats_win_lite),
1345 .enable = VOP_REG(RK3066_SYS_CTRL1, 0x1, 2),
1346 .format = VOP_REG(RK3066_SYS_CTRL0, 0x7, 10),
1347 .rb_swap = VOP_REG(RK3066_SYS_CTRL0, 0x1, 27),
1348 .dsp_info = VOP_REG(RK3066_WIN2_DSP_INFO, 0x0fff0fff, 0),
1349 .dsp_st = VOP_REG(RK3066_WIN2_DSP_ST, 0x1fff1fff, 0),
1350 .yrgb_mst = VOP_REG(RK3066_WIN2_MST, 0xffffffff, 0),
1351 .yrgb_vir = VOP_REG(RK3066_WIN2_VIR, 0xffff, 0),
1352 .alpha_mode = VOP_REG(RK3066_DSP_CTRL0, 0x1, 23),
1353 .alpha_en = VOP_REG(RK3066_BLEND_CTRL, 0x1, 2)
1354 };
1355
1356 static const struct vop_win_data rk3066_vop_win_data[] = {
1357 { .base = 0x00, .phy = &rk3066_win0_data,
1358 .type = DRM_PLANE_TYPE_PRIMARY },
1359 { .base = 0x00, .phy = &rk3066_win1_data,
1360 .type = DRM_PLANE_TYPE_OVERLAY },
1361 { .base = 0x00, .phy = &rk3066_win2_data,
1362 .type = DRM_PLANE_TYPE_CURSOR },
1363 };
1364
1365 static const int rk3066_vop_intrs[] = {
1366 0,
1367 FS_INTR,
1368 LINE_FLAG_INTR,
1369 BUS_ERROR_INTR,
1370 };
1371
1372 static const struct vop_intr rk3066_intr = {
1373 .intrs = rk3066_vop_intrs,
1374 .nintrs = ARRAY_SIZE(rk3066_vop_intrs),
1375 .line_flag_num[0] = VOP_REG(RK3066_INT_STATUS, 0xfff, 12),
1376 .status = VOP_REG(RK3066_INT_STATUS, 0xf, 0),
1377 .enable = VOP_REG(RK3066_INT_STATUS, 0xf, 4),
1378 .clear = VOP_REG(RK3066_INT_STATUS, 0xf, 8),
1379 };
1380
1381 static const struct vop_ctrl rk3066_ctrl_data = {
1382 .standby = VOP_REG(RK3066_SYS_CTRL0, 0x1, 1),
1383 .out_mode = VOP_REG(RK3066_DSP_CTRL0, 0xf, 0),
1384 .dsp_blank = VOP_REG(RK3066_DSP_CTRL1, 0x1, 24),
1385 .dclk_pol = VOP_REG(RK3066_DSP_CTRL0, 0x1, 7),
1386 .pin_pol = VOP_REG(RK3066_DSP_CTRL0, 0x7, 4),
1387 .dsp_layer_sel = VOP_REG(RK3066_DSP_CTRL0, 0x1, 8),
1388 .htotal_pw = VOP_REG(RK3066_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
1389 .hact_st_end = VOP_REG(RK3066_DSP_HACT_ST_END, 0x1fff1fff, 0),
1390 .vtotal_pw = VOP_REG(RK3066_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
1391 .vact_st_end = VOP_REG(RK3066_DSP_VACT_ST_END, 0x1fff1fff, 0),
1392 .cfg_done = VOP_REG(RK3066_REG_CFG_DONE, 0x1, 0),
1393 };
1394
1395 static const struct vop_data rk3066_vop = {
1396 .soc_id = 0x3066,
1397 .vop_id = 0,
1398 .version = VOP_VERSION(2, 1),
1399 .max_input = {1920, 4096},
1400 .max_output = {1920, 1080},
1401 .ctrl = &rk3066_ctrl_data,
1402 .intr = &rk3066_intr,
1403 .win = rk3066_vop_win_data,
1404 .win_size = ARRAY_SIZE(rk3066_vop_win_data),
1405 };
1406
1407 static const int rk3366_vop_lit_intrs[] = {
1408 FS_INTR,
1409 FS_NEW_INTR,
1410 ADDR_SAME_INTR,
1411 LINE_FLAG_INTR,
1412 LINE_FLAG1_INTR,
1413 BUS_ERROR_INTR,
1414 WIN0_EMPTY_INTR,
1415 WIN1_EMPTY_INTR,
1416 DSP_HOLD_VALID_INTR,
1417 DMA_FINISH_INTR,
1418 WIN2_EMPTY_INTR,
1419 POST_BUF_EMPTY_INTR
1420 };
1421
1422 static const struct vop_scl_regs rk3366_lit_win_scl = {
1423 .scale_yrgb_x = VOP_REG(RK3366_LIT_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
1424 .scale_yrgb_y = VOP_REG(RK3366_LIT_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
1425 .scale_cbcr_x = VOP_REG(RK3366_LIT_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
1426 .scale_cbcr_y = VOP_REG(RK3366_LIT_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
1427 };
1428
1429 static const struct vop_win_phy rk3366_lit_win0_data = {
1430 .scl = &rk3366_lit_win_scl,
1431 .data_formats = formats_win_full,
1432 .nformats = ARRAY_SIZE(formats_win_full),
1433
1434 .enable = VOP_REG(RK3366_LIT_WIN0_CTRL0, 0x1, 0),
1435 .format = VOP_REG(RK3366_LIT_WIN0_CTRL0, 0x7, 1),
1436 .interlace_read = VOP_REG(RK3366_LIT_WIN0_CTRL0, 0x1, 8),
1437 .rb_swap = VOP_REG(RK3366_LIT_WIN0_CTRL0, 0x1, 12),
1438 .act_info = VOP_REG(RK3366_LIT_WIN0_ACT_INFO, 0xffffffff, 0),
1439 .dsp_info = VOP_REG(RK3366_LIT_WIN0_DSP_INFO, 0xffffffff, 0),
1440 .dsp_st = VOP_REG(RK3366_LIT_WIN0_DSP_ST, 0xffffffff, 0),
1441 .yrgb_mst = VOP_REG(RK3366_LIT_WIN0_YRGB_MST0, 0xffffffff, 0),
1442 .uv_mst = VOP_REG(RK3366_LIT_WIN0_CBR_MST0, 0xffffffff, 0),
1443 .yrgb_vir = VOP_REG(RK3366_LIT_WIN0_VIR, 0x1fff, 0),
1444 .uv_vir = VOP_REG(RK3366_LIT_WIN0_VIR, 0x1fff, 16),
1445
1446 .alpha_pre_mul = VOP_REG(RK3366_LIT_WIN0_ALPHA_CTRL, 0x1, 2),
1447 .alpha_mode = VOP_REG(RK3366_LIT_WIN0_ALPHA_CTRL, 0x1, 1),
1448 .alpha_en = VOP_REG(RK3366_LIT_WIN0_ALPHA_CTRL, 0x1, 0),
1449 .global_alpha_val = VOP_REG(RK3366_LIT_WIN0_ALPHA_CTRL, 0xff, 4),
1450 .color_key = VOP_REG(RK3366_LIT_WIN0_COLOR_KEY, 0xffffff, 0),
1451 .color_key_en = VOP_REG(RK3366_LIT_WIN0_COLOR_KEY, 0x1, 24),
1452 .channel = VOP_REG(RK3366_LIT_WIN0_CTRL0, 0xff, 12),
1453 };
1454
1455 static const struct vop_win_phy rk3366_lit_win1_data = {
1456 .data_formats = formats_win_lite,
1457 .nformats = ARRAY_SIZE(formats_win_lite),
1458
1459 .enable = VOP_REG(RK3366_LIT_WIN1_CTRL0, 0x1, 0),
1460 .format = VOP_REG(RK3366_LIT_WIN1_CTRL0, 0x7, 4),
1461 .interlace_read = VOP_REG(RK3366_LIT_WIN1_CTRL0, 0x1, 8),
1462 .rb_swap = VOP_REG(RK3366_LIT_WIN1_CTRL0, 0x1, 12),
1463 .dsp_info = VOP_REG(RK3366_LIT_WIN1_DSP_INFO, 0xffffffff, 0),
1464 .dsp_st = VOP_REG(RK3366_LIT_WIN1_DSP_ST, 0xffffffff, 0),
1465 .yrgb_mst = VOP_REG(RK3366_LIT_WIN1_MST, 0xffffffff, 0),
1466 .yrgb_vir = VOP_REG(RK3366_LIT_WIN1_VIR, 0x1fff, 0),
1467
1468 .alpha_pre_mul = VOP_REG(RK3366_LIT_WIN1_ALPHA_CTRL, 0x1, 2),
1469 .alpha_mode = VOP_REG(RK3366_LIT_WIN1_ALPHA_CTRL, 0x1, 1),
1470 .alpha_en = VOP_REG(RK3366_LIT_WIN1_ALPHA_CTRL, 0x1, 0),
1471 .global_alpha_val = VOP_REG(RK3366_LIT_WIN1_ALPHA_CTRL, 0xff, 4),
1472 .color_key = VOP_REG(RK3366_LIT_WIN1_COLOR_KEY, 0xffffff, 0),
1473 .color_key_en = VOP_REG(RK3366_LIT_WIN1_COLOR_KEY, 0x1, 24),
1474 .channel = VOP_REG(RK3366_LIT_WIN1_CTRL1, 0xf, 8),
1475 };
1476
1477 static const struct vop_win_data rk3366_vop_lit_win_data[] = {
1478 { .base = 0x00, .phy = &rk3366_lit_win0_data,
1479 .type = DRM_PLANE_TYPE_PRIMARY },
1480 { .base = 0x00, .phy = &rk3366_lit_win1_data,
1481 .type = DRM_PLANE_TYPE_CURSOR },
1482 };
1483
1484 static const struct vop_intr rk3366_lit_intr = {
1485 .intrs = rk3366_vop_lit_intrs,
1486 .nintrs = ARRAY_SIZE(rk3366_vop_lit_intrs),
1487 .line_flag_num[0] = VOP_REG(RK3366_LIT_LINE_FLAG, 0xfff, 0),
1488 .line_flag_num[1] = VOP_REG(RK3366_LIT_LINE_FLAG, 0xfff, 16),
1489 .status = VOP_REG_MASK(RK3366_LIT_INTR_STATUS, 0xffff, 0),
1490 .enable = VOP_REG_MASK(RK3366_LIT_INTR_EN, 0xffff, 0),
1491 .clear = VOP_REG_MASK(RK3366_LIT_INTR_CLEAR, 0xffff, 0),
1492 };
1493
1494 static const struct vop_win_phy rk3126_win1_data = {
1495 .data_formats = formats_win_lite,
1496 .nformats = ARRAY_SIZE(formats_win_lite),
1497 .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1),
1498 .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6),
1499 .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19),
1500 .dsp_info = VOP_REG(RK3126_WIN1_DSP_INFO, 0x0fff0fff, 0),
1501 .dsp_st = VOP_REG(RK3126_WIN1_DSP_ST, 0x1fff1fff, 0),
1502 .yrgb_mst = VOP_REG(RK3126_WIN1_MST, 0xffffffff, 0),
1503 .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0),
1504 .alpha_mode = VOP_REG(RK3036_DSP_CTRL0, 0x1, 19),
1505 .alpha_en = VOP_REG(RK3036_ALPHA_CTRL, 0x1, 1),
1506 .alpha_pre_mul = VOP_REG(RK3036_DSP_CTRL0, 0x1, 29),
1507 };
1508
1509 static const struct vop_win_data rk3126_vop_win_data[] = {
1510 { .base = 0x00, .phy = &rk3036_win0_data,
1511 .type = DRM_PLANE_TYPE_OVERLAY },
1512 { .base = 0x00, .phy = &rk3126_win1_data,
1513 .type = DRM_PLANE_TYPE_PRIMARY },
1514 };
1515
1516 static const struct vop_data rk3126_vop = {
1517 .soc_id = 0x3126,
1518 .vop_id = 0,
1519 .version = VOP_VERSION(2, 4),
1520 .max_input = {1920, 8192},
1521 .max_output = {1920, 1080},
1522 .ctrl = &rk3036_ctrl_data,
1523 .intr = &rk3036_intr,
1524 .win = rk3126_vop_win_data,
1525 .win_size = ARRAY_SIZE(rk3126_vop_win_data),
1526 };
1527
1528 /* PX30 VOPB win2 is same with RK3368,
1529 * but RK3368 win2 register offset is 0xb0 and px30 is 0x190,
1530 * so we set the PX30 VOPB win2 base = 0x190 - 0xb0 = 0xe0
1531 */
1532
1533 static const struct vop_ctrl px30_ctrl_data = {
1534 .standby = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 1),
1535 .axi_outstanding_max_num = VOP_REG(RK3366_LIT_SYS_CTRL1, 0x1f, 16),
1536 .axi_max_outstanding_en = VOP_REG(RK3366_LIT_SYS_CTRL1, 0x1, 12),
1537 .htotal_pw = VOP_REG(RK3366_LIT_DSP_HTOTAL_HS_END, 0x0fff0fff, 0),
1538 .hact_st_end = VOP_REG(RK3366_LIT_DSP_HACT_ST_END, 0x0fff0fff, 0),
1539 .vtotal_pw = VOP_REG(RK3366_LIT_DSP_VTOTAL_VS_END, 0x0fff0fff, 0),
1540 .vact_st_end = VOP_REG(RK3366_LIT_DSP_VACT_ST_END, 0x0fff0fff, 0),
1541 .vact_st_end_f1 = VOP_REG(RK3366_LIT_DSP_VACT_ST_END_F1, 0x0fff0fff, 0),
1542 .vs_st_end_f1 = VOP_REG(RK3366_LIT_DSP_VS_ST_END_F1, 0x0fff0fff, 0),
1543 .dsp_interlace = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 0),
1544 .global_regdone_en = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 13),
1545 .auto_gate_en = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 0),
1546 .dsp_layer_sel = VOP_REG(RK3366_LIT_DSP_CTRL2, 0xff, 22),
1547 .overlay_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 4),
1548 .core_dclk_div = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 13),
1549 .dclk_ddr = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 14),
1550 .rgb_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 0),
1551 .rgb_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 2),
1552 .hdmi_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 8),
1553 .hdmi_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 10),
1554 .lvds_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 16),
1555 .lvds_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 18),
1556 .mipi_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 24),
1557 .mipi_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 26),
1558 .mipi_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 25),
1559 .lvds_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 17),
1560 .hdmi_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 9),
1561 .rgb_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 1),
1562 .dither_down_en = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 8),
1563 .dither_down_sel = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 7),
1564 .dither_down_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 6),
1565 .dither_up_en = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 2),
1566 .dsp_data_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1f, 9),
1567 .dsp_bg_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 9),
1568 .dsp_rb_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 11),
1569 .dsp_rg_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 12),
1570 .dsp_ccir656_avg = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 5),
1571 .dsp_black = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 15),
1572 .dsp_blank = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 14),
1573 .dsp_outzero = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 3),
1574 .dsp_lut_en = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 5),
1575 .out_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0xf, 16),
1576 .dsp_background = VOP_REG(RK3366_LIT_DSP_BG, 0x00ffffff, 0),
1577 .cfg_done = VOP_REG(RK3366_LIT_REG_CFG_DONE, 0x1, 0),
1578
1579 .bcsh_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 0),
1580 .bcsh_r2y_csc_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 1),
1581 .bcsh_out_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x3, 2),
1582 .bcsh_y2r_csc_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x3, 4),
1583 .bcsh_y2r_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 6),
1584 .bcsh_r2y_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 7),
1585 .bcsh_color_bar = VOP_REG(RK3366_LIT_BCSH_COL_BAR, 0xffffff, 0),
1586 .bcsh_brightness = VOP_REG(RK3366_LIT_BCSH_BCS, 0xff, 0),
1587 .bcsh_contrast = VOP_REG(RK3366_LIT_BCSH_BCS, 0x1ff, 8),
1588 .bcsh_sat_con = VOP_REG(RK3366_LIT_BCSH_BCS, 0x3ff, 20),
1589 .bcsh_sin_hue = VOP_REG(RK3366_LIT_BCSH_H, 0x1ff, 0),
1590 .bcsh_cos_hue = VOP_REG(RK3366_LIT_BCSH_H, 0x1ff, 16),
1591
1592 .afbdc_en = VOP_REG(PX30_AFBCD0_CTRL, 0x1, 0),
1593 .afbdc_format = VOP_REG(PX30_AFBCD0_CTRL, 0x1f, 4),
1594 .afbdc_pic_vir_width = VOP_REG(PX30_AFBCD0_CTRL, 0xffff, 16),
1595 .afbdc_hdr_ptr = VOP_REG(PX30_AFBCD0_HDR_PTR, 0xffffffff, 0),
1596 .afbdc_pic_size = VOP_REG(PX30_AFBCD0_PIC_SIZE, 0xffffffff, 0),
1597 .afbdc_pic_offset = VOP_REG(PX30_AFBCD0_PIC_OFFSET, 0xffffffff, 0),
1598 .afbdc_axi_ctrl = VOP_REG(PX30_AFBCD0_AXI_CTRL, 0xffffffff, 0),
1599
1600 .mcu_pix_total = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 0),
1601 .mcu_cs_pst = VOP_REG(RK3366_LIT_MCU_CTRL, 0xf, 6),
1602 .mcu_cs_pend = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 10),
1603 .mcu_rw_pst = VOP_REG(RK3366_LIT_MCU_CTRL, 0xf, 16),
1604 .mcu_rw_pend = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 20),
1605 .mcu_clk_sel = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 26),
1606 .mcu_hold_mode = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 27),
1607 .mcu_frame_st = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 28),
1608 .mcu_rs = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 29),
1609 .mcu_bypass = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 30),
1610 .mcu_type = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 31),
1611 .mcu_rw_bypass_port = VOP_REG(RK3366_LIT_MCU_RW_BYPASS_PORT,
1612 0xffffffff, 0),
1613 };
1614
1615 static const struct vop_win_phy px30_win23_data = {
1616 .data_formats = formats_win_lite,
1617 .nformats = ARRAY_SIZE(formats_win_lite),
1618 .gate = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 0),
1619 .enable = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 4),
1620 .format = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 5),
1621 .rb_swap = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 20),
1622 .dsp_info = VOP_REG(RK3368_WIN2_DSP_INFO0, 0x0fff0fff, 0),
1623 .dsp_st = VOP_REG(RK3368_WIN2_DSP_ST0, 0x1fff1fff, 0),
1624 .yrgb_mst = VOP_REG(RK3368_WIN2_MST0, 0xffffffff, 0),
1625 .yrgb_vir = VOP_REG(RK3368_WIN2_VIR0_1, 0x1fff, 0),
1626 .alpha_pre_mul = VOP_REG(RK3368_WIN2_SRC_ALPHA_CTRL, 0x1, 2),
1627 .alpha_mode = VOP_REG(RK3368_WIN2_SRC_ALPHA_CTRL, 0x1, 1),
1628 .alpha_en = VOP_REG(RK3368_WIN2_SRC_ALPHA_CTRL, 0x1, 0),
1629 .global_alpha_val = VOP_REG(RK3368_WIN2_SRC_ALPHA_CTRL, 0xff, 4),
1630 .channel = VOP_REG(RK3368_WIN2_CTRL1, 0xf, 8),
1631 .color_key = VOP_REG(RK3368_WIN2_COLOR_KEY, 0xffffff, 0),
1632 .color_key_en = VOP_REG(RK3368_WIN2_COLOR_KEY, 0x1, 24),
1633 };
1634
1635 static const struct vop_win_data px30_vop_big_win_data[] = {
1636 { .base = 0x00, .phy = &rk3366_lit_win0_data,
1637 .type = DRM_PLANE_TYPE_OVERLAY },
1638 { .base = 0x00, .phy = &rk3366_lit_win1_data,
1639 .type = DRM_PLANE_TYPE_PRIMARY,
1640 .feature = WIN_FEATURE_AFBDC },
1641 { .base = 0xe0, .phy = &px30_win23_data,
1642 .type = DRM_PLANE_TYPE_CURSOR,
1643 .area = rk3368_area_data,
1644 .area_size = ARRAY_SIZE(rk3368_area_data), },
1645 };
1646
1647 static const struct vop_win_data px30_vop_lit_win_data[] = {
1648 { .phy = NULL },
1649 { .base = 0x00, .phy = &rk3366_lit_win1_data,
1650 .type = DRM_PLANE_TYPE_PRIMARY },
1651 { .phy = NULL },
1652 };
1653
1654 static const struct vop_grf_ctrl px30_grf_ctrl = {
1655 .grf_dclk_inv = VOP_REG(PX30_GRF_PD_VO_CON1, 0x1, 4),
1656 };
1657
1658 static const struct vop_data px30_vop_lit = {
1659 .soc_id = 0x3326,
1660 .vop_id = 1,
1661 .version = VOP_VERSION(2, 5),
1662 .max_input = {1920, 8192},
1663 .max_output = {1920, 1080},
1664 .ctrl = &px30_ctrl_data,
1665 .intr = &rk3366_lit_intr,
1666 .grf_ctrl = &px30_grf_ctrl,
1667 .win = px30_vop_lit_win_data,
1668 .win_size = ARRAY_SIZE(px30_vop_lit_win_data),
1669 };
1670
1671 static const struct vop_data px30_vop_big = {
1672 .soc_id = 0x3326,
1673 .vop_id = 0,
1674 .version = VOP_VERSION(2, 6),
1675 .max_input = {1920, 8192},
1676 .max_output = {1920, 1080},
1677 .ctrl = &px30_ctrl_data,
1678 .intr = &rk3366_lit_intr,
1679 .grf_ctrl = &px30_grf_ctrl,
1680 .win = px30_vop_big_win_data,
1681 .win_size = ARRAY_SIZE(px30_vop_big_win_data),
1682 };
1683
1684 static const struct vop_ctrl rk3308_ctrl_data = {
1685 .standby = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 1),
1686 .axi_outstanding_max_num = VOP_REG(RK3366_LIT_SYS_CTRL1, 0x1f, 16),
1687 .axi_max_outstanding_en = VOP_REG(RK3366_LIT_SYS_CTRL1, 0x1, 12),
1688 .htotal_pw = VOP_REG(RK3366_LIT_DSP_HTOTAL_HS_END, 0x0fff0fff, 0),
1689 .hact_st_end = VOP_REG(RK3366_LIT_DSP_HACT_ST_END, 0x0fff0fff, 0),
1690 .vtotal_pw = VOP_REG(RK3366_LIT_DSP_VTOTAL_VS_END, 0x0fff0fff, 0),
1691 .vact_st_end = VOP_REG(RK3366_LIT_DSP_VACT_ST_END, 0x0fff0fff, 0),
1692 .vact_st_end_f1 = VOP_REG(RK3366_LIT_DSP_VACT_ST_END_F1, 0x0fff0fff, 0),
1693 .vs_st_end_f1 = VOP_REG(RK3366_LIT_DSP_VS_ST_END_F1, 0x0fff0fff, 0),
1694 .global_regdone_en = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 13),
1695 .auto_gate_en = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 0),
1696 .dsp_layer_sel = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 3),
1697 .overlay_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 4),
1698 .dclk_ddr = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 14),
1699 .rgb_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 0),
1700 .rgb_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 2),
1701 .rgb_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 1),
1702 .dither_down_en = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 8),
1703 .dither_down_sel = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 7),
1704 .dither_down_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 6),
1705 .dither_up_en = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 2),
1706 .dsp_data_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1f, 9),
1707 .dsp_bg_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 9),
1708 .dsp_rb_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 11),
1709 .dsp_rg_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 12),
1710 .dsp_ccir656_avg = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 5),
1711 .dsp_black = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 15),
1712 .dsp_blank = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 14),
1713 .dsp_outzero = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 3),
1714 .dsp_lut_en = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 5),
1715 .out_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0xf, 16),
1716 .dsp_background = VOP_REG(RK3366_LIT_DSP_BG, 0x00ffffff, 0),
1717 .cfg_done = VOP_REG(RK3366_LIT_REG_CFG_DONE, 0x1, 0),
1718
1719 .bcsh_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 0),
1720 .bcsh_r2y_csc_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 1),
1721 .bcsh_out_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x3, 2),
1722 .bcsh_y2r_csc_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x3, 4),
1723 .bcsh_y2r_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 6),
1724 .bcsh_r2y_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 7),
1725 .bcsh_color_bar = VOP_REG(RK3366_LIT_BCSH_COL_BAR, 0xffffff, 0),
1726 .bcsh_brightness = VOP_REG(RK3366_LIT_BCSH_BCS, 0x3f, 0),
1727 .bcsh_contrast = VOP_REG(RK3366_LIT_BCSH_BCS, 0xff, 8),
1728 .bcsh_sat_con = VOP_REG(RK3366_LIT_BCSH_BCS, 0x1ff, 16),
1729 .bcsh_sin_hue = VOP_REG(RK3366_LIT_BCSH_H, 0xff, 0),
1730 .bcsh_cos_hue = VOP_REG(RK3366_LIT_BCSH_H, 0xff, 8),
1731
1732 .mcu_pix_total = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 0),
1733 .mcu_cs_pst = VOP_REG(RK3366_LIT_MCU_CTRL, 0xf, 6),
1734 .mcu_cs_pend = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 10),
1735 .mcu_rw_pst = VOP_REG(RK3366_LIT_MCU_CTRL, 0xf, 16),
1736 .mcu_rw_pend = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 20),
1737 .mcu_clk_sel = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 26),
1738 .mcu_hold_mode = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 27),
1739 .mcu_frame_st = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 28),
1740 .mcu_rs = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 29),
1741 .mcu_bypass = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 30),
1742 .mcu_type = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 31),
1743 .mcu_rw_bypass_port = VOP_REG(RK3366_LIT_MCU_RW_BYPASS_PORT,
1744 0xffffffff, 0),
1745 };
1746
1747 static const int rk3308_vop_intrs[] = {
1748 FS_INTR,
1749 FS_NEW_INTR,
1750 ADDR_SAME_INTR,
1751 LINE_FLAG_INTR,
1752 LINE_FLAG1_INTR,
1753 BUS_ERROR_INTR,
1754 0,
1755 0,
1756 DSP_HOLD_VALID_INTR,
1757 DMA_FINISH_INTR,
1758 0,
1759 POST_BUF_EMPTY_INTR
1760 };
1761
1762 static const struct vop_intr rk3308_vop_intr = {
1763 .intrs = rk3308_vop_intrs,
1764 .nintrs = ARRAY_SIZE(rk3308_vop_intrs),
1765 .line_flag_num[0] = VOP_REG(RK3366_LIT_LINE_FLAG, 0xfff, 0),
1766 .line_flag_num[1] = VOP_REG(RK3366_LIT_LINE_FLAG, 0xfff, 16),
1767 .status = VOP_REG_MASK(RK3366_LIT_INTR_STATUS, 0xffff, 0),
1768 .enable = VOP_REG_MASK(RK3366_LIT_INTR_EN, 0xffff, 0),
1769 .clear = VOP_REG_MASK(RK3366_LIT_INTR_CLEAR, 0xffff, 0),
1770 };
1771
1772 static const struct vop_data rk3308_vop = {
1773 .soc_id = 0x3308,
1774 .vop_id = 0,
1775 .version = VOP_VERSION(2, 7),
1776 .max_input = {1920, 8192},
1777 .max_output = {1920, 1080},
1778 .ctrl = &rk3308_ctrl_data,
1779 .intr = &rk3308_vop_intr,
1780 .win = rk3366_vop_lit_win_data,
1781 .win_size = ARRAY_SIZE(rk3366_vop_lit_win_data),
1782 };
1783
1784 static const struct vop_ctrl rv1126_ctrl_data = {
1785 .standby = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 1),
1786 .axi_outstanding_max_num = VOP_REG(RK3366_LIT_SYS_CTRL1, 0x1f, 16),
1787 .axi_max_outstanding_en = VOP_REG(RK3366_LIT_SYS_CTRL1, 0x1, 12),
1788 .htotal_pw = VOP_REG(RK3366_LIT_DSP_HTOTAL_HS_END, 0x0fff0fff, 0),
1789 .hact_st_end = VOP_REG(RK3366_LIT_DSP_HACT_ST_END, 0x0fff0fff, 0),
1790 .vtotal_pw = VOP_REG(RK3366_LIT_DSP_VTOTAL_VS_END, 0x0fff0fff, 0),
1791 .vact_st_end = VOP_REG(RK3366_LIT_DSP_VACT_ST_END, 0x0fff0fff, 0),
1792 .vact_st_end_f1 = VOP_REG(RK3366_LIT_DSP_VACT_ST_END_F1, 0x0fff0fff, 0),
1793 .vs_st_end_f1 = VOP_REG(RK3366_LIT_DSP_VS_ST_END_F1, 0x0fff0fff, 0),
1794 .dsp_interlace = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 0),
1795 .global_regdone_en = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 13),
1796 .auto_gate_en = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 0),
1797 .dsp_layer_sel = VOP_REG(RK3366_LIT_DSP_CTRL2, 0xff, 22),
1798 .overlay_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 4),
1799 .core_dclk_div = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 13),
1800 .dclk_ddr = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 14),
1801 .rgb_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 0),
1802 .rgb_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 2),
1803 .hdmi_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 8),
1804 .hdmi_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 10),
1805 .lvds_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 16),
1806 .lvds_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 18),
1807 .mipi_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 24),
1808 .mipi_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 26),
1809 .mipi_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 25),
1810 .lvds_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 17),
1811 .hdmi_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 9),
1812 .rgb_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 1),
1813 .dither_down_en = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 8),
1814 .dither_down_sel = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 7),
1815 .dither_down_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 6),
1816 .dither_up_en = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 2),
1817 .dsp_data_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1f, 9),
1818 .dsp_bg_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 9),
1819 .dsp_rb_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 11),
1820 .dsp_rg_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 12),
1821 .yuv_clip = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 4),
1822 .dsp_ccir656_avg = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 5),
1823 .dsp_black = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 15),
1824 .dsp_blank = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 14),
1825 .dsp_outzero = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 3),
1826 .dsp_lut_en = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 5),
1827 .out_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0xf, 16),
1828 .dsp_background = VOP_REG(RK3366_LIT_DSP_BG, 0x00ffffff, 0),
1829 .cfg_done = VOP_REG(RK3366_LIT_REG_CFG_DONE, 0x1, 0),
1830
1831 .bcsh_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 0),
1832 .bcsh_r2y_csc_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 1),
1833 .bcsh_out_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x3, 2),
1834 .bcsh_y2r_csc_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x3, 4),
1835 .bcsh_y2r_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 6),
1836 .bcsh_r2y_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 7),
1837 .bcsh_color_bar = VOP_REG(RK3366_LIT_BCSH_COL_BAR, 0xffffff, 0),
1838 .bcsh_brightness = VOP_REG(RK3366_LIT_BCSH_BCS, 0xff, 0),
1839 .bcsh_contrast = VOP_REG(RK3366_LIT_BCSH_BCS, 0x1ff, 8),
1840 .bcsh_sat_con = VOP_REG(RK3366_LIT_BCSH_BCS, 0x3ff, 20),
1841 .bcsh_sin_hue = VOP_REG(RK3366_LIT_BCSH_H, 0x1ff, 0),
1842 .bcsh_cos_hue = VOP_REG(RK3366_LIT_BCSH_H, 0x1ff, 16),
1843
1844 .mcu_pix_total = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 0),
1845 .mcu_cs_pst = VOP_REG(RK3366_LIT_MCU_CTRL, 0xf, 6),
1846 .mcu_cs_pend = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 10),
1847 .mcu_rw_pst = VOP_REG(RK3366_LIT_MCU_CTRL, 0xf, 16),
1848 .mcu_rw_pend = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 20),
1849 .mcu_clk_sel = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 26),
1850 .mcu_hold_mode = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 27),
1851 .mcu_frame_st = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 28),
1852 .mcu_rs = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 29),
1853 .mcu_bypass = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 30),
1854 .mcu_type = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 31),
1855 .mcu_rw_bypass_port = VOP_REG(RK3366_LIT_MCU_RW_BYPASS_PORT,
1856 0xffffffff, 0),
1857 .bt1120_yc_swap = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 30),
1858 .bt1120_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 31),
1859 };
1860
1861 static const struct vop_win_data rv1126_vop_win_data[] = {
1862 { .base = 0x00, .phy = &rk3366_lit_win0_data,
1863 .type = DRM_PLANE_TYPE_OVERLAY },
1864 { .phy = NULL },
1865 { .base = 0xe0, .phy = &px30_win23_data,
1866 .type = DRM_PLANE_TYPE_PRIMARY,
1867 .area = rk3368_area_data,
1868 .area_size = ARRAY_SIZE(rk3368_area_data), },
1869 };
1870
1871 static const struct vop_grf_ctrl rv1126_grf_ctrl = {
1872 .grf_dclk_inv = VOP_REG(RV1126_GRF_IOFUNC_CON3, 0x1, 2),
1873 };
1874
1875 static const struct vop_data rv1126_vop = {
1876 .soc_id = 0x1126,
1877 .vop_id = 0,
1878 .version = VOP_VERSION(2, 0xb),
1879 .max_input = {1920, 1920},
1880 .max_output = {1920, 1080},
1881 .ctrl = &rv1126_ctrl_data,
1882 .intr = &rk3366_lit_intr,
1883 .grf_ctrl = &rv1126_grf_ctrl,
1884 .win = rv1126_vop_win_data,
1885 .win_size = ARRAY_SIZE(rv1126_vop_win_data),
1886 };
1887
1888 static const struct vop_ctrl rv1106_ctrl_data = {
1889 .standby = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 1),
1890 .axi_outstanding_max_num = VOP_REG(RK3366_LIT_SYS_CTRL1, 0x1f, 16),
1891 .axi_max_outstanding_en = VOP_REG(RK3366_LIT_SYS_CTRL1, 0x1, 12),
1892 .htotal_pw = VOP_REG(RK3366_LIT_DSP_HTOTAL_HS_END, 0x0fff0fff, 0),
1893 .hact_st_end = VOP_REG(RK3366_LIT_DSP_HACT_ST_END, 0x0fff0fff, 0),
1894 .vtotal_pw = VOP_REG(RK3366_LIT_DSP_VTOTAL_VS_END, 0x0fff0fff, 0),
1895 .vact_st_end = VOP_REG(RK3366_LIT_DSP_VACT_ST_END, 0x0fff0fff, 0),
1896 .vact_st_end_f1 = VOP_REG(RK3366_LIT_DSP_VACT_ST_END_F1, 0x0fff0fff, 0),
1897 .vs_st_end_f1 = VOP_REG(RK3366_LIT_DSP_VS_ST_END_F1, 0x0fff0fff, 0),
1898 .dsp_interlace = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 0),
1899 .auto_gate_en = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 0),
1900 .overlay_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 4),
1901 .core_dclk_div = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 13),
1902 .dclk_ddr = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 14),
1903 .rgb_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 0),
1904 .rgb_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 1),
1905 .dither_down_en = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 8),
1906 .dither_down_sel = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 7),
1907 .dither_down_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 6),
1908 .dither_up_en = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 2),
1909 .dsp_data_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1f, 9),
1910 .dsp_bg_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 9),
1911 .dsp_rb_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 11),
1912 .dsp_rg_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 12),
1913 .yuv_clip = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 4),
1914 .dsp_black = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 15),
1915 .dsp_blank = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 14),
1916 .dsp_outzero = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 3),
1917 .out_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0xf, 16),
1918 .dsp_background = VOP_REG(RK3366_LIT_DSP_BG, 0x00ffffff, 0),
1919 .cfg_done = VOP_REG(RK3366_LIT_REG_CFG_DONE, 0x1, 0),
1920
1921 .bcsh_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 0),
1922 .bcsh_r2y_csc_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 1),
1923 .bcsh_out_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x3, 2),
1924 .bcsh_y2r_csc_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x3, 4),
1925 .bcsh_y2r_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 6),
1926 .bcsh_r2y_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 7),
1927 .bcsh_color_bar = VOP_REG(RK3366_LIT_BCSH_COL_BAR, 0xffffff, 0),
1928 .bcsh_brightness = VOP_REG(RK3366_LIT_BCSH_BCS, 0xff, 0),
1929 .bcsh_contrast = VOP_REG(RK3366_LIT_BCSH_BCS, 0x1ff, 8),
1930 .bcsh_sat_con = VOP_REG(RK3366_LIT_BCSH_BCS, 0x3ff, 20),
1931 .bcsh_sin_hue = VOP_REG(RK3366_LIT_BCSH_H, 0x1ff, 0),
1932 .bcsh_cos_hue = VOP_REG(RK3366_LIT_BCSH_H, 0x1ff, 16),
1933
1934 .mcu_pix_total = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 0),
1935 .mcu_cs_pst = VOP_REG(RK3366_LIT_MCU_CTRL, 0xf, 6),
1936 .mcu_cs_pend = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 10),
1937 .mcu_rw_pst = VOP_REG(RK3366_LIT_MCU_CTRL, 0xf, 16),
1938 .mcu_rw_pend = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 20),
1939 .mcu_clk_sel = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 26),
1940 .mcu_hold_mode = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 27),
1941 .mcu_frame_st = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 28),
1942 .mcu_rs = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 29),
1943 .mcu_bypass = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 30),
1944 .mcu_type = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 31),
1945 .mcu_rw_bypass_port = VOP_REG(RK3366_LIT_MCU_RW_BYPASS_PORT,
1946 0xffffffff, 0),
1947 .bt1120_yc_swap = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 30),
1948 .bt1120_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 31),
1949 .bt656_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 6),
1950 };
1951
1952 static const struct vop_win_data rv1106_vop_win_data[] = {
1953 { .phy = NULL },
1954 { .base = 0x00, .phy = &rk3366_lit_win1_data,
1955 .type = DRM_PLANE_TYPE_PRIMARY },
1956 };
1957
1958 static const struct vop_grf_ctrl rv1106_grf_ctrl = {
1959 .grf_dclk_inv = VOP_REG(RV1106_VENC_GRF_VOP_IO_WRAPPER, 0x1, 2),
1960 };
1961
1962 static const struct vop_data rv1106_vop = {
1963 .soc_id = 0x1106,
1964 .vop_id = 0,
1965 .version = VOP_VERSION(2, 0xc),
1966 .max_input = {1280, 1280},
1967 .max_output = {1280, 1280},
1968 .ctrl = &rv1106_ctrl_data,
1969 .intr = &rk3366_lit_intr,
1970 .grf_ctrl = &rv1106_grf_ctrl,
1971 .win = rv1106_vop_win_data,
1972 .win_size = ARRAY_SIZE(rv1106_vop_win_data),
1973 };
1974
1975 static const struct of_device_id vop_driver_dt_match[] = {
1976 #if IS_ENABLED(CONFIG_CPU_RK3036)
1977 { .compatible = "rockchip,rk3036-vop",
1978 .data = &rk3036_vop },
1979 #endif
1980 #if IS_ENABLED(CONFIG_CPU_RK30XX)
1981 { .compatible = "rockchip,rk3066-vop",
1982 .data = &rk3066_vop },
1983 #endif
1984 #if IS_ENABLED(CONFIG_CPU_RK312X)
1985 { .compatible = "rockchip,rk3126-vop",
1986 .data = &rk3126_vop },
1987 #endif
1988 #if IS_ENABLED(CONFIG_CPU_PX30)
1989 { .compatible = "rockchip,px30-vop-lit",
1990 .data = &px30_vop_lit },
1991 { .compatible = "rockchip,px30-vop-big",
1992 .data = &px30_vop_big },
1993 #endif
1994 #if IS_ENABLED(CONFIG_CPU_RK3308)
1995 { .compatible = "rockchip,rk3308-vop",
1996 .data = &rk3308_vop },
1997 #endif
1998 #if IS_ENABLED(CONFIG_CPU_RV1106)
1999 { .compatible = "rockchip,rv1106-vop",
2000 .data = &rv1106_vop },
2001 #endif
2002 #if IS_ENABLED(CONFIG_CPU_RV1126)
2003 { .compatible = "rockchip,rv1126-vop",
2004 .data = &rv1126_vop },
2005 #endif
2006 #if IS_ENABLED(CONFIG_CPU_RK3288)
2007 { .compatible = "rockchip,rk3288-vop-big",
2008 .data = &rk3288_vop_big },
2009 { .compatible = "rockchip,rk3288-vop-lit",
2010 .data = &rk3288_vop_lit },
2011 #endif
2012 #if IS_ENABLED(CONFIG_CPU_RK3368)
2013 { .compatible = "rockchip,rk3368-vop",
2014 .data = &rk3368_vop },
2015 { .compatible = "rockchip,rk3366-vop",
2016 .data = &rk3366_vop },
2017 #endif
2018 #if IS_ENABLED(CONFIG_CPU_RK3399)
2019 { .compatible = "rockchip,rk3399-vop-big",
2020 .data = &rk3399_vop_big },
2021 { .compatible = "rockchip,rk3399-vop-lit",
2022 .data = &rk3399_vop_lit },
2023 #endif
2024 #if IS_ENABLED(CONFIG_CPU_RK322X)
2025 { .compatible = "rockchip,rk3228-vop",
2026 .data = &rk3228_vop },
2027 #endif
2028 #if IS_ENABLED(CONFIG_CPU_RK3328)
2029 { .compatible = "rockchip,rk3328-vop",
2030 .data = &rk3328_vop },
2031 #endif
2032 {},
2033 };
2034 MODULE_DEVICE_TABLE(of, vop_driver_dt_match);
2035
vop_probe(struct platform_device * pdev)2036 static int vop_probe(struct platform_device *pdev)
2037 {
2038 struct device *dev = &pdev->dev;
2039
2040 if (!dev->of_node) {
2041 DRM_DEV_ERROR(dev, "can't find vop devices\n");
2042 return -ENODEV;
2043 }
2044
2045 return component_add(dev, &vop_component_ops);
2046 }
2047
vop_remove(struct platform_device * pdev)2048 static int vop_remove(struct platform_device *pdev)
2049 {
2050 component_del(&pdev->dev, &vop_component_ops);
2051
2052 return 0;
2053 }
2054
2055 struct platform_driver vop_platform_driver = {
2056 .probe = vop_probe,
2057 .remove = vop_remove,
2058 .driver = {
2059 .name = "rockchip-vop",
2060 .of_match_table = of_match_ptr(vop_driver_dt_match),
2061 },
2062 };
2063