1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2021 Rockchip Electronics Co., Ltd 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #include <common.h> 8*4882a593Smuzhiyun #include <dm.h> 9*4882a593Smuzhiyun #include <syscon.h> 10*4882a593Smuzhiyun #include <asm/arch/clock.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun static const struct udevice_id rk3588_syscon_ids[] = { 13*4882a593Smuzhiyun { .compatible = "rockchip,rk3588-sys-grf", .data = ROCKCHIP_SYSCON_GRF }, 14*4882a593Smuzhiyun { .compatible = "rockchip,rk3588-vop-grf", .data = ROCKCHIP_SYSCON_VOP_GRF }, 15*4882a593Smuzhiyun { .compatible = "rockchip,rk3588-vo-grf", .data = ROCKCHIP_SYSCON_VO_GRF }, 16*4882a593Smuzhiyun { .compatible = "rockchip,pcie30-phy-grf", .data = ROCKCHIP_SYSCON_PCIE30_PHY_GRF }, 17*4882a593Smuzhiyun { .compatible = "rockchip,rk3588-php-grf", .data = ROCKCHIP_SYSCON_PHP_GRF }, 18*4882a593Smuzhiyun { .compatible = "rockchip,pipe-phy-grf", .data = ROCKCHIP_SYSCON_PIPE_PHY0_GRF }, 19*4882a593Smuzhiyun { .compatible = "rockchip,pipe-phy-grf", .data = ROCKCHIP_SYSCON_PIPE_PHY1_GRF }, 20*4882a593Smuzhiyun { .compatible = "rockchip,pipe-phy-grf", .data = ROCKCHIP_SYSCON_PIPE_PHY2_GRF }, 21*4882a593Smuzhiyun { .compatible = "rockchip,rk3588-pmu", .data = ROCKCHIP_SYSCON_PMU }, 22*4882a593Smuzhiyun { } 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun U_BOOT_DRIVER(syscon_rk3588) = { 26*4882a593Smuzhiyun .name = "rk3588_syscon", 27*4882a593Smuzhiyun .id = UCLASS_SYSCON, 28*4882a593Smuzhiyun .of_match = rk3588_syscon_ids, 29*4882a593Smuzhiyun #if !CONFIG_IS_ENABLED(OF_PLATDATA) 30*4882a593Smuzhiyun .bind = dm_scan_fdt_dev, 31*4882a593Smuzhiyun #endif 32*4882a593Smuzhiyun }; 33