1*4882a593SmuzhiyunRockchip PWM controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun - compatible: should be "rockchip,<name>-pwm" 5*4882a593Smuzhiyun "rockchip,rk2928-pwm": found on RK29XX,RK3066 and RK3188 SoCs 6*4882a593Smuzhiyun "rockchip,rk3288-pwm": found on RK3288 SOC 7*4882a593Smuzhiyun "rockchip,rv1108-pwm", "rockchip,rk3288-pwm": found on RV1108 SoC 8*4882a593Smuzhiyun "rockchip,vop-pwm": found integrated in VOP on RK3288 SoC 9*4882a593Smuzhiyun - reg: physical base address and length of the controller's registers 10*4882a593Smuzhiyun - clocks: See ../clock/clock-bindings.txt 11*4882a593Smuzhiyun - For older hardware (rk2928, rk3066, rk3188, rk3228, rk3288, rk3399): 12*4882a593Smuzhiyun - There is one clock that's used both to derive the functional clock 13*4882a593Smuzhiyun for the device and as the bus clock. 14*4882a593Smuzhiyun - For newer hardware (rk3328 and future socs): specified by name 15*4882a593Smuzhiyun - "pwm": This is used to derive the functional clock. 16*4882a593Smuzhiyun - "pclk": This is the APB bus clock. 17*4882a593Smuzhiyun - #pwm-cells: must be 2 (rk2928) or 3 (rk3288). See pwm.yaml in this directory 18*4882a593Smuzhiyun for a description of the cell format. 19*4882a593Smuzhiyun 20*4882a593SmuzhiyunExample: 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun pwm0: pwm@20030000 { 23*4882a593Smuzhiyun compatible = "rockchip,rk2928-pwm"; 24*4882a593Smuzhiyun reg = <0x20030000 0x10>; 25*4882a593Smuzhiyun clocks = <&cru PCLK_PWM01>; 26*4882a593Smuzhiyun #pwm-cells = <2>; 27*4882a593Smuzhiyun }; 28