xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.yaml (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun%YAML 1.2
3*4882a593Smuzhiyun---
4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/display/rockchip/rockchip-vop.yaml#
5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml#
6*4882a593Smuzhiyun
7*4882a593Smuzhiyuntitle: Rockchip SoC display controller (VOP)
8*4882a593Smuzhiyun
9*4882a593Smuzhiyundescription:
10*4882a593Smuzhiyun  VOP (Video Output Processor) is the display controller for the Rockchip
11*4882a593Smuzhiyun  series of SoCs which transfers the image data from a video memory
12*4882a593Smuzhiyun  buffer to an external LCD interface.
13*4882a593Smuzhiyun
14*4882a593Smuzhiyunmaintainers:
15*4882a593Smuzhiyun  - Sandy Huang <hjc@rock-chips.com>
16*4882a593Smuzhiyun  - Heiko Stuebner <heiko@sntech.de>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyunproperties:
19*4882a593Smuzhiyun  compatible:
20*4882a593Smuzhiyun    enum:
21*4882a593Smuzhiyun      - rockchip,px30-vop-big
22*4882a593Smuzhiyun      - rockchip,px30-vop-lit
23*4882a593Smuzhiyun      - rockchip,rk3036-vop
24*4882a593Smuzhiyun      - rockchip,rk3066-vop
25*4882a593Smuzhiyun      - rockchip,rk3126-vop
26*4882a593Smuzhiyun      - rockchip,rk3188-vop
27*4882a593Smuzhiyun      - rockchip,rk3228-vop
28*4882a593Smuzhiyun      - rockchip,rk3288-vop
29*4882a593Smuzhiyun      - rockchip,rk3328-vop
30*4882a593Smuzhiyun      - rockchip,rk3366-vop
31*4882a593Smuzhiyun      - rockchip,rk3368-vop
32*4882a593Smuzhiyun      - rockchip,rk3399-vop-big
33*4882a593Smuzhiyun      - rockchip,rk3399-vop-lit
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun  reg:
36*4882a593Smuzhiyun    minItems: 1
37*4882a593Smuzhiyun    items:
38*4882a593Smuzhiyun      - description:
39*4882a593Smuzhiyun          Must contain one entry corresponding to the base address and length
40*4882a593Smuzhiyun          of the register space.
41*4882a593Smuzhiyun      - description:
42*4882a593Smuzhiyun          Can optionally contain a second entry corresponding to
43*4882a593Smuzhiyun          the CRTC gamma LUT address.
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun  interrupts:
46*4882a593Smuzhiyun    maxItems: 1
47*4882a593Smuzhiyun    description:
48*4882a593Smuzhiyun      The VOP interrupt is shared by several interrupt sources, such as
49*4882a593Smuzhiyun      frame start (VSYNC), line flag and other status interrupts.
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun  clocks:
52*4882a593Smuzhiyun    items:
53*4882a593Smuzhiyun      - description: Clock for ddr buffer transfer.
54*4882a593Smuzhiyun      - description: Pixel clock.
55*4882a593Smuzhiyun      - description: Clock for the ahb bus to R/W the phy regs.
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun  clock-names:
58*4882a593Smuzhiyun    items:
59*4882a593Smuzhiyun      - const: aclk_vop
60*4882a593Smuzhiyun      - const: dclk_vop
61*4882a593Smuzhiyun      - const: hclk_vop
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun  resets:
64*4882a593Smuzhiyun    maxItems: 3
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun  reset-names:
67*4882a593Smuzhiyun    items:
68*4882a593Smuzhiyun      - const: axi
69*4882a593Smuzhiyun      - const: ahb
70*4882a593Smuzhiyun      - const: dclk
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun  port:
73*4882a593Smuzhiyun    type: object
74*4882a593Smuzhiyun    description:
75*4882a593Smuzhiyun      A port node with endpoint definitions as defined in
76*4882a593Smuzhiyun      Documentation/devicetree/bindings/media/video-interfaces.txt.
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun  assigned-clocks:
79*4882a593Smuzhiyun    maxItems: 2
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun  assigned-clock-rates:
82*4882a593Smuzhiyun    maxItems: 2
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun  iommus:
85*4882a593Smuzhiyun    maxItems: 1
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun  power-domains:
88*4882a593Smuzhiyun    maxItems: 1
89*4882a593Smuzhiyun
90*4882a593Smuzhiyunrequired:
91*4882a593Smuzhiyun  - compatible
92*4882a593Smuzhiyun  - reg
93*4882a593Smuzhiyun  - interrupts
94*4882a593Smuzhiyun  - clocks
95*4882a593Smuzhiyun  - clock-names
96*4882a593Smuzhiyun  - resets
97*4882a593Smuzhiyun  - reset-names
98*4882a593Smuzhiyun  - port
99*4882a593Smuzhiyun
100*4882a593SmuzhiyunadditionalProperties: false
101*4882a593Smuzhiyun
102*4882a593Smuzhiyunexamples:
103*4882a593Smuzhiyun  - |
104*4882a593Smuzhiyun    #include <dt-bindings/clock/rk3288-cru.h>
105*4882a593Smuzhiyun    #include <dt-bindings/interrupt-controller/arm-gic.h>
106*4882a593Smuzhiyun    #include <dt-bindings/power/rk3288-power.h>
107*4882a593Smuzhiyun    vopb: vopb@ff930000 {
108*4882a593Smuzhiyun      compatible = "rockchip,rk3288-vop";
109*4882a593Smuzhiyun      reg = <0xff930000 0x19c>,
110*4882a593Smuzhiyun            <0xff931000 0x1000>;
111*4882a593Smuzhiyun      interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
112*4882a593Smuzhiyun      clocks = <&cru ACLK_VOP0>,
113*4882a593Smuzhiyun               <&cru DCLK_VOP0>,
114*4882a593Smuzhiyun               <&cru HCLK_VOP0>;
115*4882a593Smuzhiyun      clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
116*4882a593Smuzhiyun      power-domains = <&power RK3288_PD_VIO>;
117*4882a593Smuzhiyun      resets = <&cru SRST_LCDC1_AXI>,
118*4882a593Smuzhiyun               <&cru SRST_LCDC1_AHB>,
119*4882a593Smuzhiyun               <&cru SRST_LCDC1_DCLK>;
120*4882a593Smuzhiyun      reset-names = "axi", "ahb", "dclk";
121*4882a593Smuzhiyun      iommus = <&vopb_mmu>;
122*4882a593Smuzhiyun      vopb_out: port {
123*4882a593Smuzhiyun        #address-cells = <1>;
124*4882a593Smuzhiyun        #size-cells = <0>;
125*4882a593Smuzhiyun        vopb_out_edp: endpoint@0 {
126*4882a593Smuzhiyun          reg = <0>;
127*4882a593Smuzhiyun          remote-endpoint=<&edp_in_vopb>;
128*4882a593Smuzhiyun        };
129*4882a593Smuzhiyun        vopb_out_hdmi: endpoint@1 {
130*4882a593Smuzhiyun          reg = <1>;
131*4882a593Smuzhiyun          remote-endpoint=<&hdmi_in_vopb>;
132*4882a593Smuzhiyun        };
133*4882a593Smuzhiyun      };
134*4882a593Smuzhiyun    };
135