1*4882a593SmuzhiyunRockchip RGB interface 2*4882a593Smuzhiyun================================ 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunRequired properties: 5*4882a593Smuzhiyun- compatible: matching the soc type: 6*4882a593Smuzhiyun - "rockchip,px30-rgb"; 7*4882a593Smuzhiyun - "rockchip,rk1808-rgb"; 8*4882a593Smuzhiyun - "rockchip,rk3066-rgb"; 9*4882a593Smuzhiyun - "rockchip,rk3128-rgb"; 10*4882a593Smuzhiyun - "rockchip,rk3288-rgb"; 11*4882a593Smuzhiyun - "rockchip,rk3308-rgb"; 12*4882a593Smuzhiyun - "rockchip,rk3368-rgb"; 13*4882a593Smuzhiyun - "rockchip,rv1108-rgb"; 14*4882a593Smuzhiyun - "rockchip,rv1126-rgb"; 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunOptional properties: 17*4882a593Smuzhiyun- phys : phandle for the PHY device 18*4882a593Smuzhiyun- phy-names : should be "phy" 19*4882a593Smuzhiyun- pinctrl-names: the pin control state names; should contain "default" 20*4882a593Smuzhiyun- pinctrl-0: the default pinctrl state (active) 21*4882a593Smuzhiyun- pinctrl-1: the "sleep" pinctrl state 22*4882a593Smuzhiyun- rockchip,data-sync-bypass: bypass the vop data-sync logic from io 23*4882a593Smuzhiyun 24*4882a593SmuzhiyunThe rgb has two video ports described by: 25*4882a593Smuzhiyun Documentation/devicetree/bindings/media/video-interfaces.txt 26*4882a593SmuzhiyunTheir connections are modeled using the OF graph bindings specified in 27*4882a593Smuzhiyun Documentation/devicetree/bindings/graph.txt. 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun- video port 0 for the VOP input 30*4882a593Smuzhiyun- video port 1 for either a panel or bridge 31*4882a593Smuzhiyun 32*4882a593SmuzhiyunExample: 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun&grf { 35*4882a593Smuzhiyun rgb: rgb { 36*4882a593Smuzhiyun compatible = "rockchip,rk3288-rgb"; 37*4882a593Smuzhiyun pinctrl-names = "default", "sleep"; 38*4882a593Smuzhiyun pinctrl-0 = <&lcdc_rgb_pins>; 39*4882a593Smuzhiyun pinctrl-1 = <&lcdc_sleep_pins>; 40*4882a593Smuzhiyun phys = <&video_phy>; 41*4882a593Smuzhiyun phy-names = "phy"; 42*4882a593Smuzhiyun status = "disabled"; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun ports { 45*4882a593Smuzhiyun #address-cells = <1>; 46*4882a593Smuzhiyun #size-cells = <0>; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun port@0 { 49*4882a593Smuzhiyun reg = <0>; 50*4882a593Smuzhiyun #address-cells = <1>; 51*4882a593Smuzhiyun #size-cells = <0>; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun rgb_in_vopb: endpoint@0 { 54*4882a593Smuzhiyun reg = <0>; 55*4882a593Smuzhiyun remote-endpoint = <&vopb_out_rgb>; 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun rgb_in_vopl: endpoint@1 { 59*4882a593Smuzhiyun reg = <1>; 60*4882a593Smuzhiyun remote-endpoint = <&vopl_out_rgb>; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun}; 66