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/rk3399_ARM-atf/fdts/
H A Dstm32mp251.dtsi96 clocks = <&rcc CK_KER_USART2>;
97 resets = <&rcc USART2_R>;
104 clocks = <&rcc CK_KER_USART3>;
105 resets = <&rcc USART3_R>;
112 clocks = <&rcc CK_KER_UART4>;
113 resets = <&rcc UART4_R>;
120 clocks = <&rcc CK_KER_UART5>;
121 resets = <&rcc UART5_R>;
128 clocks = <&rcc CK_KER_I2C1>;
129 resets = <&rcc I2C1_R>;
[all …]
H A Dstm32mp151.dtsi84 clocks = <&rcc TIM12_K>;
93 clocks = <&rcc USART2_K>;
94 resets = <&rcc USART2_R>;
102 clocks = <&rcc USART3_K>;
103 resets = <&rcc USART3_R>;
111 clocks = <&rcc UART4_K>;
112 resets = <&rcc UART4_R>;
121 clocks = <&rcc UART5_K>;
122 resets = <&rcc UART5_R>;
132 clocks = <&rcc I2C2_K>;
[all …]
H A Dstm32mp131.dtsi22 clocks = <&rcc CK_MPU>;
85 clocks = <&rcc USART3_K>;
86 resets = <&rcc USART3_R>;
94 clocks = <&rcc UART4_K>;
95 resets = <&rcc UART4_R>;
103 clocks = <&rcc UART5_K>;
104 resets = <&rcc UART5_R>;
112 clocks = <&rcc UART7_K>;
113 resets = <&rcc UART7_R>;
121 clocks = <&rcc UART8_K>;
[all …]
H A Dstm32mp211.dtsi6 #include <dt-bindings/clock/st,stm32mp21-rcc.h>
8 #include <dt-bindings/reset/st,stm32mp21-rcc.h>
131 clocks = <&rcc CK_KER_USART2>;
132 resets = <&rcc USART2_R>;
139 clocks = <&rcc CK_KER_USART3>;
140 resets = <&rcc USART3_R>;
147 clocks = <&rcc CK_KER_UART4>;
148 resets = <&rcc UART4_R>;
155 clocks = <&rcc CK_KER_UART5>;
156 resets = <&rcc UART5_R>;
[all …]
H A Dstm32mp231.dtsi130 clocks = <&rcc CK_BUS_OSPIIOM>;
131 resets = <&rcc OSPIIOM_R>;
140 clocks = <&rcc CK_KER_OSPI1>;
141 resets = <&rcc OSPI1_R>, <&rcc OSPI1DLL_R>;
148 clocks = <&rcc CK_KER_OSPI2>;
149 resets = <&rcc OSPI2_R>, <&rcc OSPI2DLL_R>;
163 clocks = <&rcc CK_KER_USART2>;
164 resets = <&rcc USART2_R>;
171 clocks = <&rcc CK_KER_USART3>;
172 resets = <&rcc USART3_R>;
[all …]
H A Dstm32mp21xf.dtsi12 clocks = <&rcc CK_BUS_CRYP1>;
13 resets = <&rcc CRYP1_R>;
20 clocks = <&rcc CK_BUS_CRYP2>;
21 resets = <&rcc CRYP2_R>;
28 clocks = <&rcc CK_BUS_SAES>;
29 resets = <&rcc SAES_R>;
36 clocks = <&rcc CK_BUS_PKA>;
37 resets = <&rcc PKA_R>;
H A Dstm32mp21xc.dtsi12 clocks = <&rcc CK_BUS_CRYP1>;
13 resets = <&rcc CRYP1_R>;
20 clocks = <&rcc CK_BUS_CRYP2>;
21 resets = <&rcc CRYP2_R>;
28 clocks = <&rcc CK_BUS_SAES>;
29 resets = <&rcc SAES_R>;
36 clocks = <&rcc CK_BUS_PKA>;
37 resets = <&rcc PKA_R>;
H A Dstm32mp23xf.dtsi12 clocks = <&rcc CK_BUS_CRYP1>;
13 resets = <&rcc CRYP1_R>;
20 clocks = <&rcc CK_BUS_CRYP2>;
21 resets = <&rcc CRYP2_R>;
28 clocks = <&rcc CK_BUS_SAES>;
29 resets = <&rcc SAES_R>;
36 clocks = <&rcc CK_BUS_PKA>;
37 resets = <&rcc PKA_R>;
H A Dstm32mp23xc.dtsi12 clocks = <&rcc CK_BUS_CRYP1>;
13 resets = <&rcc CRYP1_R>;
20 clocks = <&rcc CK_BUS_CRYP2>;
21 resets = <&rcc CRYP2_R>;
28 clocks = <&rcc CK_BUS_SAES>;
29 resets = <&rcc SAES_R>;
36 clocks = <&rcc CK_BUS_PKA>;
37 resets = <&rcc PKA_R>;
H A Dstm32mp13xf.dtsi13 clocks = <&rcc SAES_K>;
14 resets = <&rcc SAES_R>;
21 clocks = <&rcc PKA>;
22 resets = <&rcc PKA_R>;
H A Dstm32mp13xc.dtsi14 clocks = <&rcc SAES_K>;
15 resets = <&rcc SAES_R>;
22 clocks = <&rcc PKA>;
23 resets = <&rcc PKA_R>;
H A Dstm32mp15xc.dtsi13 clocks = <&rcc CRYP1>;
14 resets = <&rcc CRYP1_R>;
H A Dstm32mp153.dtsi15 clocks = <&rcc CK_MPU>;
H A Dstm32mp157c-ed1-sp_min.dts12 &rcc {
H A Dstm32mp157c-dk2-sp_min.dts12 &rcc {
H A Dstm32mp157a-dk1-sp_min.dts12 &rcc {
H A Dstm32mp257d-ultra-fly-sbc-ca35tdcid-rcc.dtsi28 &rcc {
H A Dstm32mp215f-dk-ca35tdcid-rcc.dtsi33 &rcc {
H A Dstm32mp235f-dk-ca35tdcid-rcc.dtsi32 &rcc {
H A Dstm32mp257f-dk-ca35tdcid-rcc.dtsi33 &rcc {
H A Dstm32mp257f-ev1-ca35tdcid-rcc.dtsi33 &rcc {
/rk3399_ARM-atf/drivers/st/ddr/
H A Dstm32mp2_ddr.c214 mmio_setbits_32(priv->rcc + RCC_DDRITFCFGR, RCC_DDRITFCFGR_DDRRST); in ddr_reset()
215 mmio_write_32(priv->rcc + RCC_DDRPHYCAPBCFGR, in ddr_reset()
218 mmio_write_32(priv->rcc + RCC_DDRCAPBCFGR, in ddr_reset()
221 mmio_write_32(priv->rcc + RCC_DDRCFGR, in ddr_reset()
226 mmio_setbits_32(priv->rcc + RCC_DDRITFCFGR, RCC_DDRITFCFGR_DDRRST); in ddr_reset()
227 mmio_write_32(priv->rcc + RCC_DDRPHYCAPBCFGR, in ddr_reset()
229 mmio_write_32(priv->rcc + RCC_DDRCAPBCFGR, in ddr_reset()
231 mmio_write_32(priv->rcc + RCC_DDRCFGR, RCC_DDRCFGR_DDRCFGEN | RCC_DDRCFGR_DDRCFGLPEN); in ddr_reset()
240 mmio_write_32(priv->rcc + RCC_DDRCPCFGR, in ddr_standby_reset()
242 mmio_setbits_32(priv->rcc + RCC_DDRITFCFGR, RCC_DDRITFCFGR_DDRRST); in ddr_standby_reset()
[all …]
H A Dstm32mp1_ram.c93 mmio_clrbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_AXIDCGEN); in stm32mp1_ddr_setup()
98 mmio_setbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_AXIDCGEN); in stm32mp1_ddr_setup()
148 priv->rcc = stm32mp_rcc_base(); in stm32mp1_ddr_probe()
H A Dstm32mp1_ddr.c603 mmio_setbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAPBRST); in stm32mp1_ddr_init()
604 mmio_setbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAXIRST); in stm32mp1_ddr_init()
605 mmio_setbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCORERST); in stm32mp1_ddr_init()
606 mmio_setbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYAPBRST); in stm32mp1_ddr_init()
607 mmio_setbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYRST); in stm32mp1_ddr_init()
608 mmio_setbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYCTLRST); in stm32mp1_ddr_init()
617 mmio_clrbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYRST); in stm32mp1_ddr_init()
618 mmio_clrbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYCTLRST); in stm32mp1_ddr_init()
623 mmio_clrbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAPBRST); in stm32mp1_ddr_init()
665 mmio_clrbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCORERST); in stm32mp1_ddr_init()
[all …]
/rk3399_ARM-atf/include/drivers/st/
H A Dstm32mp_ddr.h53 uintptr_t rcc; member

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