1*20544d66SYann Gautier// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2*20544d66SYann Gautier/* 3*20544d66SYann Gautier * Copyright (c) 2025, STMicroelectronics - All Rights Reserved 4*20544d66SYann Gautier */ 5*20544d66SYann Gautier 6*20544d66SYann Gautier#include "stm32mp157c-ed1.dts" 7*20544d66SYann Gautier 8*20544d66SYann Gautier/ { 9*20544d66SYann Gautier model = "STMicroelectronics STM32MP157C eval daughter (SP_MIN)"; 10*20544d66SYann Gautier}; 11*20544d66SYann Gautier 12*20544d66SYann Gautier&rcc { 13*20544d66SYann Gautier st,clksrc = < 14*20544d66SYann Gautier CLK_MPU_PLL1P 15*20544d66SYann Gautier CLK_AXI_PLL2P 16*20544d66SYann Gautier CLK_MCU_PLL3P 17*20544d66SYann Gautier CLK_RTC_LSE 18*20544d66SYann Gautier CLK_MCO1_DISABLED 19*20544d66SYann Gautier CLK_MCO2_DISABLED 20*20544d66SYann Gautier CLK_CKPER_HSE 21*20544d66SYann Gautier CLK_FMC_ACLK 22*20544d66SYann Gautier CLK_QSPI_ACLK 23*20544d66SYann Gautier CLK_ETH_PLL4P 24*20544d66SYann Gautier CLK_SDMMC12_PLL4P 25*20544d66SYann Gautier CLK_DSI_DSIPLL 26*20544d66SYann Gautier CLK_STGEN_HSE 27*20544d66SYann Gautier CLK_USBPHY_HSE 28*20544d66SYann Gautier CLK_SPI2S1_PLL3Q 29*20544d66SYann Gautier CLK_SPI2S23_PLL3Q 30*20544d66SYann Gautier CLK_SPI45_HSI 31*20544d66SYann Gautier CLK_SPI6_HSI 32*20544d66SYann Gautier CLK_I2C46_HSI 33*20544d66SYann Gautier CLK_SDMMC3_PLL4P 34*20544d66SYann Gautier CLK_USBO_USBPHY 35*20544d66SYann Gautier CLK_ADC_CKPER 36*20544d66SYann Gautier CLK_CEC_LSE 37*20544d66SYann Gautier CLK_I2C12_HSI 38*20544d66SYann Gautier CLK_I2C35_HSI 39*20544d66SYann Gautier CLK_UART1_HSI 40*20544d66SYann Gautier CLK_UART24_HSI 41*20544d66SYann Gautier CLK_UART35_HSI 42*20544d66SYann Gautier CLK_UART6_HSI 43*20544d66SYann Gautier CLK_UART78_HSI 44*20544d66SYann Gautier CLK_SPDIF_PLL4P 45*20544d66SYann Gautier CLK_FDCAN_PLL4R 46*20544d66SYann Gautier CLK_SAI1_PLL3Q 47*20544d66SYann Gautier CLK_SAI2_PLL3Q 48*20544d66SYann Gautier CLK_SAI3_PLL3Q 49*20544d66SYann Gautier CLK_SAI4_PLL3Q 50*20544d66SYann Gautier CLK_RNG1_CSI 51*20544d66SYann Gautier CLK_RNG2_LSI 52*20544d66SYann Gautier CLK_LPTIM1_PCLK1 53*20544d66SYann Gautier CLK_LPTIM23_PCLK3 54*20544d66SYann Gautier CLK_LPTIM45_LSE 55*20544d66SYann Gautier >; 56*20544d66SYann Gautier 57*20544d66SYann Gautier st,clkdiv = < 58*20544d66SYann Gautier DIV(DIV_MPU, 1) 59*20544d66SYann Gautier DIV(DIV_AXI, 0) 60*20544d66SYann Gautier DIV(DIV_MCU, 0) 61*20544d66SYann Gautier DIV(DIV_APB1, 1) 62*20544d66SYann Gautier DIV(DIV_APB2, 1) 63*20544d66SYann Gautier DIV(DIV_APB3, 1) 64*20544d66SYann Gautier DIV(DIV_APB4, 1) 65*20544d66SYann Gautier DIV(DIV_APB5, 2) 66*20544d66SYann Gautier DIV(DIV_MCO1, 0) 67*20544d66SYann Gautier DIV(DIV_MCO2, 0) 68*20544d66SYann Gautier >; 69*20544d66SYann Gautier}; 70