1*a4e31cf0SBoerge Struempfel// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) 2*a4e31cf0SBoerge Struempfel/* 3*a4e31cf0SBoerge Struempfel * Copyright (C) 2025, Ultratronik GmbH 4*a4e31cf0SBoerge Struempfel * Copyright (C) STMicroelectronics 2025 - All Rights Reserved 5*a4e31cf0SBoerge Struempfel * Author: Boerge Struempfel <boerge.struempfel@gmail.com> for Ultratronik GmbH. 6*a4e31cf0SBoerge Struempfel */ 7*a4e31cf0SBoerge Struempfel 8*a4e31cf0SBoerge Struempfel&clk_hse { 9*a4e31cf0SBoerge Struempfel clock-frequency = <40000000>; 10*a4e31cf0SBoerge Struempfel}; 11*a4e31cf0SBoerge Struempfel 12*a4e31cf0SBoerge Struempfel&clk_hsi { 13*a4e31cf0SBoerge Struempfel clock-frequency = <64000000>; 14*a4e31cf0SBoerge Struempfel}; 15*a4e31cf0SBoerge Struempfel 16*a4e31cf0SBoerge Struempfel&clk_lse { 17*a4e31cf0SBoerge Struempfel clock-frequency = <32768>; 18*a4e31cf0SBoerge Struempfel}; 19*a4e31cf0SBoerge Struempfel 20*a4e31cf0SBoerge Struempfel&clk_lsi { 21*a4e31cf0SBoerge Struempfel clock-frequency = <32000>; 22*a4e31cf0SBoerge Struempfel}; 23*a4e31cf0SBoerge Struempfel 24*a4e31cf0SBoerge Struempfel&clk_msi { 25*a4e31cf0SBoerge Struempfel clock-frequency = <16000000>; 26*a4e31cf0SBoerge Struempfel}; 27*a4e31cf0SBoerge Struempfel 28*a4e31cf0SBoerge Struempfel&rcc { 29*a4e31cf0SBoerge Struempfel st,busclk = < 30*a4e31cf0SBoerge Struempfel DIV_CFG(DIV_LSMCU, 1) 31*a4e31cf0SBoerge Struempfel DIV_CFG(DIV_APB1, 0) 32*a4e31cf0SBoerge Struempfel DIV_CFG(DIV_APB2, 0) 33*a4e31cf0SBoerge Struempfel DIV_CFG(DIV_APB3, 0) 34*a4e31cf0SBoerge Struempfel DIV_CFG(DIV_APB4, 0) 35*a4e31cf0SBoerge Struempfel DIV_CFG(DIV_APBDBG, 0) 36*a4e31cf0SBoerge Struempfel >; 37*a4e31cf0SBoerge Struempfel 38*a4e31cf0SBoerge Struempfel st,flexgen = < 39*a4e31cf0SBoerge Struempfel FLEXGEN_CFG(0, XBAR_SRC_PLL4, 0, 2) 40*a4e31cf0SBoerge Struempfel FLEXGEN_CFG(1, XBAR_SRC_PLL4, 0, 5) 41*a4e31cf0SBoerge Struempfel FLEXGEN_CFG(2, XBAR_SRC_PLL4, 0, 1) 42*a4e31cf0SBoerge Struempfel FLEXGEN_CFG(4, XBAR_SRC_PLL4, 0, 3) 43*a4e31cf0SBoerge Struempfel FLEXGEN_CFG(5, XBAR_SRC_PLL4, 0, 2) 44*a4e31cf0SBoerge Struempfel FLEXGEN_CFG(19, XBAR_SRC_HSI_KER, 0, 0) 45*a4e31cf0SBoerge Struempfel FLEXGEN_CFG(48, XBAR_SRC_PLL5, 0, 3) 46*a4e31cf0SBoerge Struempfel FLEXGEN_CFG(51, XBAR_SRC_PLL4, 0, 5) 47*a4e31cf0SBoerge Struempfel FLEXGEN_CFG(52, XBAR_SRC_PLL4, 0, 5) 48*a4e31cf0SBoerge Struempfel FLEXGEN_CFG(58, XBAR_SRC_HSE_KER, 0, 1) 49*a4e31cf0SBoerge Struempfel FLEXGEN_CFG(63, XBAR_SRC_PLL4, 0, 2) 50*a4e31cf0SBoerge Struempfel >; 51*a4e31cf0SBoerge Struempfel 52*a4e31cf0SBoerge Struempfel st,kerclk = < 53*a4e31cf0SBoerge Struempfel MUX_CFG(MUX_USB2PHY1, MUX_USB2PHY1_FLEX57) 54*a4e31cf0SBoerge Struempfel MUX_CFG(MUX_USB2PHY2, MUX_USB2PHY2_FLEX58) 55*a4e31cf0SBoerge Struempfel >; 56*a4e31cf0SBoerge Struempfel 57*a4e31cf0SBoerge Struempfel pll1: st,pll-1 { 58*a4e31cf0SBoerge Struempfel st,pll = <&pll1_cfg_1200Mhz>; 59*a4e31cf0SBoerge Struempfel 60*a4e31cf0SBoerge Struempfel pll1_cfg_1200Mhz: pll1-cfg-1200Mhz { 61*a4e31cf0SBoerge Struempfel cfg = <30 1 1 1>; 62*a4e31cf0SBoerge Struempfel src = <MUX_CFG(MUX_MUXSEL5, MUXSEL_HSE)>; 63*a4e31cf0SBoerge Struempfel }; 64*a4e31cf0SBoerge Struempfel }; 65*a4e31cf0SBoerge Struempfel 66*a4e31cf0SBoerge Struempfel pll2: st,pll-2 { 67*a4e31cf0SBoerge Struempfel st,pll = <&pll2_cfg_600Mhz>; 68*a4e31cf0SBoerge Struempfel 69*a4e31cf0SBoerge Struempfel pll2_cfg_600Mhz: pll2-cfg-600Mhz { 70*a4e31cf0SBoerge Struempfel cfg = <30 1 1 2>; 71*a4e31cf0SBoerge Struempfel src = <MUX_CFG(MUX_MUXSEL6, MUXSEL_HSE)>; 72*a4e31cf0SBoerge Struempfel }; 73*a4e31cf0SBoerge Struempfel }; 74*a4e31cf0SBoerge Struempfel 75*a4e31cf0SBoerge Struempfel pll4: st,pll-4 { 76*a4e31cf0SBoerge Struempfel st,pll = <&pll4_cfg_1200Mhz>; 77*a4e31cf0SBoerge Struempfel 78*a4e31cf0SBoerge Struempfel pll4_cfg_1200Mhz: pll4-cfg-1200Mhz { 79*a4e31cf0SBoerge Struempfel cfg = <30 1 1 1>; 80*a4e31cf0SBoerge Struempfel src = <MUX_CFG(MUX_MUXSEL0, MUXSEL_HSE)>; 81*a4e31cf0SBoerge Struempfel }; 82*a4e31cf0SBoerge Struempfel }; 83*a4e31cf0SBoerge Struempfel 84*a4e31cf0SBoerge Struempfel pll5: st,pll-5 { 85*a4e31cf0SBoerge Struempfel st,pll = <&pll5_cfg_532Mhz>; 86*a4e31cf0SBoerge Struempfel 87*a4e31cf0SBoerge Struempfel pll5_cfg_532Mhz: pll5-cfg-532Mhz { 88*a4e31cf0SBoerge Struempfel cfg = <133 5 1 2>; 89*a4e31cf0SBoerge Struempfel src = <MUX_CFG(MUX_MUXSEL1, MUXSEL_HSE)>; 90*a4e31cf0SBoerge Struempfel }; 91*a4e31cf0SBoerge Struempfel }; 92*a4e31cf0SBoerge Struempfel}; 93