1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2/* 3 * Copyright (c) 2026, STMicroelectronics - All Rights Reserved 4 * Author: Loic Pallardy loic.pallardy@foss.st.com for STMicroelectronics. 5 */ 6 7/* 8 * stm32mp215f Clock tree device tree configuration 9 * Project : open 10 * Generated by XLmx tool version 2.2 - 10/2/2024 3:58:35 PM 11 */ 12 13&clk_hse { 14 clock-frequency = <40000000>; 15}; 16 17&clk_hsi { 18 clock-frequency = <64000000>; 19}; 20 21&clk_lse { 22 clock-frequency = <32768>; 23}; 24 25&clk_lsi { 26 clock-frequency = <32000>; 27}; 28 29&clk_msi { 30 clock-frequency = <16000000>; 31}; 32 33&rcc { 34 st,busclk = < 35 DIV_CFG(DIV_LSMCU, 1) 36 DIV_CFG(DIV_APB1, 0) 37 DIV_CFG(DIV_APB2, 0) 38 DIV_CFG(DIV_APB3, 0) 39 DIV_CFG(DIV_APB4, 0) 40 DIV_CFG(DIV_APB5, 0) 41 DIV_CFG(DIV_APBDBG, 0) 42 >; 43 44 st,flexgen = < 45 FLEXGEN_CFG(0, XBAR_SRC_PLL4, 0, 3) 46 FLEXGEN_CFG(1, XBAR_SRC_PLL4, 0, 5) 47 FLEXGEN_CFG(2, XBAR_SRC_PLL4, 0, 1) 48 FLEXGEN_CFG(4, XBAR_SRC_PLL4, 0, 3) 49 FLEXGEN_CFG(5, XBAR_SRC_PLL4, 0, 2) 50 FLEXGEN_CFG(8, XBAR_SRC_HSI_KER, 0, 0) 51 FLEXGEN_CFG(51, XBAR_SRC_PLL4, 0, 5) 52 FLEXGEN_CFG(52, XBAR_SRC_PLL4, 0, 5) 53 FLEXGEN_CFG(58, XBAR_SRC_HSE_KER, 0, 1) 54 FLEXGEN_CFG(63, XBAR_SRC_PLL4, 0, 2) 55 >; 56 57 st,kerclk = < 58 MUX_CFG(MUX_USB2PHY1, MUX_USB2PHY1_FLEX57) 59 MUX_CFG(MUX_USB2PHY2, MUX_USB2PHY2_FLEX58) 60 >; 61 62 pll1: st,pll-1 { 63 st,pll = <&pll1_cfg_1200MHz>; 64 65 pll1_cfg_1200MHz: pll1-cfg-1200MHz { 66 cfg = <30 1 1 1>; 67 src = <MUX_CFG(MUX_MUXSEL5, MUXSEL_HSE)>; 68 }; 69 }; 70 71 pll2: st,pll-2 { 72 st,pll = <&pll2_cfg_400MHz>; 73 74 pll2_cfg_400MHz: pll2-cfg-400MHz { 75 cfg = <20 1 1 2>; 76 src = <MUX_CFG(MUX_MUXSEL6, MUXSEL_HSE)>; 77 }; 78 }; 79 80 pll4: st,pll-4 { 81 st,pll = <&pll4_cfg_1200MHz>; 82 83 pll4_cfg_1200MHz: pll4-cfg-1200MHz { 84 cfg = <30 1 1 1>; 85 src = <MUX_CFG(MUX_MUXSEL0, MUXSEL_HSE)>; 86 }; 87 }; 88}; 89