1*293a4f3dSYann Gautier// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2*293a4f3dSYann Gautier/* 3*293a4f3dSYann Gautier * Copyright (C) STMicroelectronics 2024 - All Rights Reserved 4*293a4f3dSYann Gautier * Author: Loic Pallardy loic.pallardy@foss.st.com for STMicroelectronics. 5*293a4f3dSYann Gautier */ 6*293a4f3dSYann Gautier 7*293a4f3dSYann Gautier/* 8*293a4f3dSYann Gautier * STM32MP25 Clock tree device tree configuration 9*293a4f3dSYann Gautier * Project : open 10*293a4f3dSYann Gautier * Generated by XLmx tool version 2.2 - 2/27/2024 11:46:16 AM 11*293a4f3dSYann Gautier */ 12*293a4f3dSYann Gautier 13*293a4f3dSYann Gautier&clk_hse { 14*293a4f3dSYann Gautier clock-frequency = <40000000>; 15*293a4f3dSYann Gautier}; 16*293a4f3dSYann Gautier 17*293a4f3dSYann Gautier&clk_hsi { 18*293a4f3dSYann Gautier clock-frequency = <64000000>; 19*293a4f3dSYann Gautier}; 20*293a4f3dSYann Gautier 21*293a4f3dSYann Gautier&clk_lse { 22*293a4f3dSYann Gautier clock-frequency = <32768>; 23*293a4f3dSYann Gautier}; 24*293a4f3dSYann Gautier 25*293a4f3dSYann Gautier&clk_lsi { 26*293a4f3dSYann Gautier clock-frequency = <32000>; 27*293a4f3dSYann Gautier}; 28*293a4f3dSYann Gautier 29*293a4f3dSYann Gautier&clk_msi { 30*293a4f3dSYann Gautier clock-frequency = <16000000>; 31*293a4f3dSYann Gautier}; 32*293a4f3dSYann Gautier 33*293a4f3dSYann Gautier&rcc { 34*293a4f3dSYann Gautier st,busclk = < 35*293a4f3dSYann Gautier DIV_CFG(DIV_LSMCU, 1) 36*293a4f3dSYann Gautier DIV_CFG(DIV_APB1, 0) 37*293a4f3dSYann Gautier DIV_CFG(DIV_APB2, 0) 38*293a4f3dSYann Gautier DIV_CFG(DIV_APB3, 0) 39*293a4f3dSYann Gautier DIV_CFG(DIV_APB4, 0) 40*293a4f3dSYann Gautier DIV_CFG(DIV_APBDBG, 0) 41*293a4f3dSYann Gautier >; 42*293a4f3dSYann Gautier 43*293a4f3dSYann Gautier st,flexgen = < 44*293a4f3dSYann Gautier FLEXGEN_CFG(0, XBAR_SRC_PLL4, 0, 2) 45*293a4f3dSYann Gautier FLEXGEN_CFG(1, XBAR_SRC_PLL4, 0, 5) 46*293a4f3dSYann Gautier FLEXGEN_CFG(2, XBAR_SRC_PLL4, 0, 1) 47*293a4f3dSYann Gautier FLEXGEN_CFG(4, XBAR_SRC_PLL4, 0, 3) 48*293a4f3dSYann Gautier FLEXGEN_CFG(5, XBAR_SRC_PLL4, 0, 2) 49*293a4f3dSYann Gautier FLEXGEN_CFG(8, XBAR_SRC_HSI_KER, 0, 0) 50*293a4f3dSYann Gautier FLEXGEN_CFG(48, XBAR_SRC_PLL5, 0, 3) 51*293a4f3dSYann Gautier FLEXGEN_CFG(51, XBAR_SRC_PLL4, 0, 5) 52*293a4f3dSYann Gautier FLEXGEN_CFG(52, XBAR_SRC_PLL4, 0, 5) 53*293a4f3dSYann Gautier FLEXGEN_CFG(58, XBAR_SRC_HSE, 0, 1) 54*293a4f3dSYann Gautier FLEXGEN_CFG(63, XBAR_SRC_PLL4, 0, 2) 55*293a4f3dSYann Gautier >; 56*293a4f3dSYann Gautier 57*293a4f3dSYann Gautier st,kerclk = < 58*293a4f3dSYann Gautier MUX_CFG(MUX_USB2PHY1, MUX_USB2PHY1_FLEX57) 59*293a4f3dSYann Gautier MUX_CFG(MUX_USB2PHY2, MUX_USB2PHY2_FLEX58) 60*293a4f3dSYann Gautier >; 61*293a4f3dSYann Gautier 62*293a4f3dSYann Gautier pll1: st,pll-1 { 63*293a4f3dSYann Gautier st,pll = <&pll1_cfg_1200Mhz>; 64*293a4f3dSYann Gautier 65*293a4f3dSYann Gautier pll1_cfg_1200Mhz: pll1-cfg-1200Mhz { 66*293a4f3dSYann Gautier cfg = <30 1 1 1>; 67*293a4f3dSYann Gautier src = <MUX_CFG(MUX_MUXSEL5, MUXSEL_HSE)>; 68*293a4f3dSYann Gautier }; 69*293a4f3dSYann Gautier }; 70*293a4f3dSYann Gautier 71*293a4f3dSYann Gautier pll2: st,pll-2 { 72*293a4f3dSYann Gautier st,pll = <&pll2_cfg_600Mhz>; 73*293a4f3dSYann Gautier 74*293a4f3dSYann Gautier pll2_cfg_600Mhz: pll2-cfg-600Mhz { 75*293a4f3dSYann Gautier cfg = <30 1 1 2>; 76*293a4f3dSYann Gautier src = <MUX_CFG(MUX_MUXSEL6, MUXSEL_HSE)>; 77*293a4f3dSYann Gautier }; 78*293a4f3dSYann Gautier }; 79*293a4f3dSYann Gautier 80*293a4f3dSYann Gautier pll4: st,pll-4 { 81*293a4f3dSYann Gautier st,pll = <&pll4_cfg_1200Mhz>; 82*293a4f3dSYann Gautier 83*293a4f3dSYann Gautier pll4_cfg_1200Mhz: pll4-cfg-1200Mhz { 84*293a4f3dSYann Gautier cfg = <30 1 1 1>; 85*293a4f3dSYann Gautier src = <MUX_CFG(MUX_MUXSEL0, MUXSEL_HSE)>; 86*293a4f3dSYann Gautier }; 87*293a4f3dSYann Gautier }; 88*293a4f3dSYann Gautier 89*293a4f3dSYann Gautier pll5: st,pll-5 { 90*293a4f3dSYann Gautier st,pll = <&pll5_cfg_532Mhz>; 91*293a4f3dSYann Gautier 92*293a4f3dSYann Gautier pll5_cfg_532Mhz: pll5-cfg-532Mhz { 93*293a4f3dSYann Gautier cfg = <133 5 1 2>; 94*293a4f3dSYann Gautier src = <MUX_CFG(MUX_MUXSEL1, MUXSEL_HSE)>; 95*293a4f3dSYann Gautier }; 96*293a4f3dSYann Gautier }; 97*293a4f3dSYann Gautier}; 98