1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2/* 3 * Copyright (C) 2026, STMicroelectronics - All Rights Reserved 4 */ 5 6/* 7 * stm32mp235f Clock tree device tree configuration 8 * Project : open 9 * Generated by XLmx tool version 2.2 - 5/16/2024 11:06:20 AM 10 */ 11 12&clk_hse { 13 clock-frequency = <40000000>; 14}; 15 16&clk_hsi { 17 clock-frequency = <64000000>; 18}; 19 20&clk_lse { 21 clock-frequency = <32768>; 22}; 23 24&clk_lsi { 25 clock-frequency = <32000>; 26}; 27 28&clk_msi { 29 clock-frequency = <16000000>; 30}; 31 32&rcc { 33 st,busclk = < 34 DIV_CFG(DIV_LSMCU, 1) 35 DIV_CFG(DIV_APB1, 0) 36 DIV_CFG(DIV_APB2, 0) 37 DIV_CFG(DIV_APB3, 0) 38 DIV_CFG(DIV_APB4, 0) 39 DIV_CFG(DIV_APBDBG, 0) 40 >; 41 42 st,flexgen = < 43 FLEXGEN_CFG(0, XBAR_SRC_PLL4, 0, 2) 44 FLEXGEN_CFG(1, XBAR_SRC_PLL4, 0, 5) 45 FLEXGEN_CFG(2, XBAR_SRC_PLL4, 0, 1) 46 FLEXGEN_CFG(4, XBAR_SRC_PLL4, 0, 3) 47 FLEXGEN_CFG(5, XBAR_SRC_PLL4, 0, 2) 48 FLEXGEN_CFG(8, XBAR_SRC_HSI_KER, 0, 0) 49 FLEXGEN_CFG(51, XBAR_SRC_PLL4, 0, 5) 50 FLEXGEN_CFG(52, XBAR_SRC_PLL4, 0, 5) 51 FLEXGEN_CFG(58, XBAR_SRC_HSE_KER, 0, 1) 52 FLEXGEN_CFG(63, XBAR_SRC_PLL4, 0, 2) 53 >; 54 55 st,kerclk = < 56 MUX_CFG(MUX_USB2PHY1, MUX_USB2PHY1_FLEX57) 57 MUX_CFG(MUX_USB2PHY2, MUX_USB2PHY2_FLEX58) 58 >; 59 60 pll1: st,pll-1 { 61 st,pll = <&pll1_cfg_1200Mhz>; 62 63 pll1_cfg_1200Mhz: pll1-cfg-1200Mhz { 64 cfg = <30 1 1 1>; 65 src = <MUX_CFG(MUX_MUXSEL5, MUXSEL_HSE)>; 66 }; 67 }; 68 69 pll2: st,pll-2 { 70 st,pll = <&pll2_cfg_600Mhz>; 71 72 pll2_cfg_600Mhz: pll2-cfg-600Mhz { 73 cfg = <30 1 1 2>; 74 src = <MUX_CFG(MUX_MUXSEL6, MUXSEL_HSE)>; 75 }; 76 }; 77 78 pll4: st,pll-4 { 79 st,pll = <&pll4_cfg_1200Mhz>; 80 81 pll4_cfg_1200Mhz: pll4-cfg-1200Mhz { 82 cfg = <30 1 1 1>; 83 src = <MUX_CFG(MUX_MUXSEL0, MUXSEL_HSE)>; 84 }; 85 }; 86 87 pll5: st,pll-5 { 88 st,pll = <&pll5_cfg_532Mhz>; 89 90 pll5_cfg_532Mhz: pll5-cfg-532Mhz { 91 cfg = <133 5 1 2>; 92 src = <MUX_CFG(MUX_MUXSEL1, MUXSEL_HSE)>; 93 }; 94 }; 95}; 96