1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2/* 3 * Copyright (C) 2026, STMicroelectronics - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. 5 */ 6 7#include <dt-bindings/clock/stm32mp25-clks.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/reset/stm32mp25-resets.h> 10 11/ { 12 #address-cells = <2>; 13 #size-cells = <2>; 14 15 cpus { 16 #address-cells = <1>; 17 #size-cells = <0>; 18 19 cpu0: cpu@0 { 20 compatible = "arm,cortex-a35"; 21 device_type = "cpu"; 22 reg = <0>; 23 enable-method = "psci"; 24 }; 25 26 domain-idle-states { 27 domain-stop1 { 28 compatible = "domain-idle-state"; 29 arm,psci-suspend-param = <0x00000011>; 30 }; 31 32 domain-lp-stop1 { 33 compatible = "domain-idle-state"; 34 arm,psci-suspend-param = <0x00000021>; 35 }; 36 37 domain-lplv-stop1 { 38 compatible = "domain-idle-state"; 39 arm,psci-suspend-param = <0x00000211>; 40 }; 41 42 domain-stop2 { 43 compatible = "domain-idle-state"; 44 arm,psci-suspend-param = <0x40001333>; 45 }; 46 47 domain-lp-stop2 { 48 compatible = "domain-idle-state"; 49 arm,psci-suspend-param = <0x40002333>; 50 }; 51 52 domain-lplv-stop2 { 53 compatible = "domain-idle-state"; 54 arm,psci-suspend-param = <0x40023333>; 55 }; 56 57 domain-standby { 58 compatible = "domain-idle-state"; 59 arm,psci-suspend-param = <0x40033333>; 60 }; 61 }; 62 }; 63 64 clocks { 65 clk_hse: clk-hse { 66 #clock-cells = <0>; 67 compatible = "fixed-clock"; 68 clock-frequency = <48000000>; 69 }; 70 71 clk_hsi: clk-hsi { 72 #clock-cells = <0>; 73 compatible = "fixed-clock"; 74 clock-frequency = <64000000>; 75 }; 76 77 clk_lse: clk-lse { 78 #clock-cells = <0>; 79 compatible = "fixed-clock"; 80 clock-frequency = <32768>; 81 }; 82 83 clk_lsi: clk-lsi { 84 #clock-cells = <0>; 85 compatible = "fixed-clock"; 86 clock-frequency = <32000>; 87 }; 88 89 clk_msi: clk-msi { 90 #clock-cells = <0>; 91 compatible = "fixed-clock"; 92 clock-frequency = <16000000>; 93 }; 94 }; 95 96 intc: interrupt-controller@4ac00000 { 97 compatible = "arm,cortex-a7-gic"; 98 #interrupt-cells = <3>; 99 #address-cells = <1>; 100 interrupt-controller; 101 reg = <0x0 0x4ac10000 0x0 0x1000>, 102 <0x0 0x4ac20000 0x0 0x2000>, 103 <0x0 0x4ac40000 0x0 0x2000>, 104 <0x0 0x4ac60000 0x0 0x2000>; 105 }; 106 107 timer { 108 compatible = "arm,armv8-timer"; 109 interrupt-parent = <&intc>; 110 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 111 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 112 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 113 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 114 always-on; 115 }; 116 117 soc@0 { 118 compatible = "simple-bus"; 119 #address-cells = <1>; 120 #size-cells = <1>; 121 interrupt-parent = <&intc>; 122 ranges = <0x0 0x0 0x0 0x80000000>; 123 124 ommanager: ommanager@40500000 { 125 #address-cells = <2>; 126 #size-cells = <1>; 127 compatible = "st,stm32mp25-omm"; 128 reg = <0x40500000 0x400>, <0x60000000 0x10000000>; 129 reg-names = "omm", "omm_mm"; 130 clocks = <&rcc CK_BUS_OSPIIOM>; 131 resets = <&rcc OSPIIOM_R>; 132 status = "disabled"; 133 134 ranges = <0 0 0x40430000 0x400>, 135 <1 0 0x40440000 0x400>; 136 137 ospi1: spi@40430000 { 138 compatible = "st,stm32mp25-omi"; 139 reg = <0 0 0x400>; 140 clocks = <&rcc CK_KER_OSPI1>; 141 resets = <&rcc OSPI1_R>, <&rcc OSPI1DLL_R>; 142 status = "disabled"; 143 }; 144 145 ospi2: spi@40440000 { 146 compatible = "st,stm32mp25-omi"; 147 reg = <1 0 0x400>; 148 clocks = <&rcc CK_KER_OSPI2>; 149 resets = <&rcc OSPI2_R>, <&rcc OSPI2DLL_R>; 150 status = "disabled"; 151 }; 152 }; 153 154 rifsc: rifsc@42080000 { 155 compatible = "st,stm32mp25-rifsc", "syscon"; 156 reg = <0x42080000 0x1000>; 157 #address-cells = <1>; 158 #size-cells = <1>; 159 160 usart2: serial@400e0000 { 161 compatible = "st,stm32h7-uart"; 162 reg = <0x400e0000 0x400>; 163 clocks = <&rcc CK_KER_USART2>; 164 resets = <&rcc USART2_R>; 165 status = "disabled"; 166 }; 167 168 usart3: serial@400f0000 { 169 compatible = "st,stm32h7-uart"; 170 reg = <0x400f0000 0x400>; 171 clocks = <&rcc CK_KER_USART3>; 172 resets = <&rcc USART3_R>; 173 status = "disabled"; 174 }; 175 176 uart4: serial@40100000 { 177 compatible = "st,stm32h7-uart"; 178 reg = <0x40100000 0x400>; 179 clocks = <&rcc CK_KER_UART4>; 180 resets = <&rcc UART4_R>; 181 status = "disabled"; 182 }; 183 184 uart5: serial@40110000 { 185 compatible = "st,stm32h7-uart"; 186 reg = <0x40110000 0x400>; 187 clocks = <&rcc CK_KER_UART5>; 188 resets = <&rcc UART5_R>; 189 status = "disabled"; 190 }; 191 192 i2c1: i2c@40120000 { 193 compatible = "st,stm32mp25-i2c"; 194 reg = <0x40120000 0x400>; 195 clocks = <&rcc CK_KER_I2C1>; 196 resets = <&rcc I2C1_R>; 197 status = "disabled"; 198 }; 199 200 i2c2: i2c@40130000 { 201 compatible = "st,stm32mp25-i2c"; 202 reg = <0x40130000 0x400>; 203 clocks = <&rcc CK_KER_I2C2>; 204 resets = <&rcc I2C2_R>; 205 status = "disabled"; 206 }; 207 208 i2c7: i2c@40180000 { 209 compatible = "st,stm32mp25-i2c"; 210 reg = <0x40180000 0x400>; 211 clocks = <&rcc CK_KER_I2C7>; 212 resets = <&rcc I2C7_R>; 213 status = "disabled"; 214 }; 215 216 usart6: serial@40220000 { 217 compatible = "st,stm32h7-uart"; 218 reg = <0x40220000 0x400>; 219 clocks = <&rcc CK_KER_USART6>; 220 resets = <&rcc USART6_R>; 221 status = "disabled"; 222 }; 223 224 usart1: serial@40330000 { 225 compatible = "st,stm32h7-uart"; 226 reg = <0x40330000 0x400>; 227 clocks = <&rcc CK_KER_USART1>; 228 resets = <&rcc USART1_R>; 229 status = "disabled"; 230 }; 231 232 uart7: serial@40370000 { 233 compatible = "st,stm32h7-uart"; 234 reg = <0x40370000 0x400>; 235 clocks = <&rcc CK_KER_UART7>; 236 resets = <&rcc UART7_R>; 237 status = "disabled"; 238 }; 239 240 hash: hash@42010000 { 241 compatible = "st,stm32mp13-hash"; 242 reg = <0x42010000 0x400>; 243 clocks = <&rcc CK_BUS_HASH>; 244 resets = <&rcc HASH_R>; 245 status = "disabled"; 246 }; 247 248 rng: rng@42020000 { 249 compatible = "st,stm32mp13-rng"; 250 reg = <0x42020000 0x400>; 251 clocks = <&rcc CK_BUS_RNG>; 252 resets = <&rcc RNG_R>; 253 status = "disabled"; 254 }; 255 256 iwdg1: watchdog@44010000 { 257 compatible = "st,stm32mp1-iwdg"; 258 reg = <0x44010000 0x400>; 259 clocks = <&rcc CK_BUS_IWDG1>, <&rcc LSI_CK>; 260 clock-names = "pclk", "lsi"; 261 status = "disabled"; 262 }; 263 264 i2c8: i2c@46040000 { 265 compatible = "st,stm32mp25-i2c"; 266 reg = <0x46040000 0x400>; 267 clocks = <&rcc CK_KER_I2C8>; 268 resets = <&rcc I2C8_R>; 269 status = "disabled"; 270 }; 271 272 sdmmc1: mmc@48220000 { 273 compatible = "st,stm32mp25-sdmmc2", "arm,pl18x", "arm,primecell"; 274 arm,primecell-periphid = <0x00353180>; 275 reg = <0x48220000 0x400>, <0x44230400 0x8>; 276 clocks = <&rcc CK_KER_SDMMC1>; 277 clock-names = "apb_pclk"; 278 resets = <&rcc SDMMC1_R>; 279 cap-sd-highspeed; 280 cap-mmc-highspeed; 281 max-frequency = <166000000>; 282 status = "disabled"; 283 }; 284 285 sdmmc2: mmc@48230000 { 286 compatible = "st,stm32mp25-sdmmc2", "arm,pl18x", "arm,primecell"; 287 arm,primecell-periphid = <0x00353180>; 288 reg = <0x48230000 0x400>, <0x44230800 0x8>; 289 clocks = <&rcc CK_KER_SDMMC2>; 290 clock-names = "apb_pclk"; 291 resets = <&rcc SDMMC2_R>; 292 cap-sd-highspeed; 293 cap-mmc-highspeed; 294 max-frequency = <166000000>; 295 status = "disabled"; 296 }; 297 }; 298 299 risaf2: risaf@420b0000 { 300 compatible = "st,stm32-risaf"; 301 reg = <0x420b0000 0x1000>; 302 clocks = <&rcc CK_KER_OSPI1>; 303 status = "disabled"; 304 }; 305 306 risaf4: risaf@420d0000 { 307 compatible = "st,stm32-risaf"; 308 reg = <0x420d0000 0x1000>; 309 clocks = <&rcc CK_BUS_RISAF4>; 310 status = "disabled"; 311 }; 312 313 bsec: efuse@44000000 { 314 compatible = "st,stm32mp25-bsec"; 315 reg = <0x44000000 0x400>; 316 #address-cells = <1>; 317 #size-cells = <1>; 318 319 uid_otp: uid-otp@14 { 320 reg = <0x14 0xc>; 321 }; 322 part_number_otp: part-number-otp@24 { 323 reg = <0x24 0x4>; 324 }; 325 nand_otp: otp16@40 { 326 reg = <0x40 0x4>; 327 }; 328 lifecycle2_otp: otp18@48 { 329 reg = <0x48 0x4>; 330 }; 331 nand2_otp: otp20@50 { 332 reg = <0x50 0x4>; 333 }; 334 rev_otp@198 { 335 reg = <0x198 0x4>; 336 }; 337 package_otp: package-otp@1e8 { 338 reg = <0x1e8 0x1>; 339 }; 340 hconf1_otp: otp124@1f0 { 341 reg = <0x1f0 0x4>; 342 }; 343 pkh_otp: otp144@240 { 344 reg = <0x240 0x20>; 345 }; 346 oem_fip_enc_key: otp260@410 { 347 reg = <0x410 0x20>; 348 }; 349 }; 350 351 rcc: clock-controller@44200000 { 352 compatible = "st,stm32mp25-rcc"; 353 reg = <0x44200000 0x10000>; 354 #clock-cells = <1>; 355 #reset-cells = <1>; 356 }; 357 358 pwr: pwr@44210000 { 359 compatible = "st,stm32mp25-pwr"; 360 reg = <0x44210000 0x400>; 361 362 vddio1: vddio1 { 363 regulator-name = "vddio1"; 364 }; 365 366 vddio2: vddio2 { 367 regulator-name = "vddio2"; 368 }; 369 370 vddio3: vddio3 { 371 regulator-name = "vddio3"; 372 }; 373 374 vddio4: vddio4 { 375 regulator-name = "vddio4"; 376 }; 377 378 vddio: vddio { 379 regulator-name = "vddio"; 380 }; 381 }; 382 383 syscfg: syscon@44230000 { 384 compatible = "st,stm32mp25-syscfg", "syscon"; 385 reg = <0x44230000 0x10000>; 386 }; 387 388 tamp: tamp@46010000 { 389 compatible = "st,stm32mp25-tamp"; 390 reg = <0x46010000 0x400>; 391 clocks = <&rcc CK_BUS_RTC>; 392 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 393 #address-cells = <1>; 394 #size-cells = <1>; 395 ranges; 396 397 nvram: nvram@46010100 { 398 compatible = "st,stm32mp25-tamp-nvram"; 399 #address-cells = <1>; 400 #size-cells = <1>; 401 reg = <0x46010100 0x200>; 402 403 stop2_entrypoint: tamp-bkp@2c { 404 reg = <0x2c 0x4>; 405 }; 406 fwu_info: tamp-bkp@c0 { 407 /* see firmware update info feature */ 408 reg = <0xc0 0x4>; 409 }; 410 boot_mode: tamp-bkp@180 { 411 reg = <0x180 0x4>; 412 }; 413 414 }; 415 416 boot_info: boot-info { 417 compatible = "st,stm32mp-bootinfo"; 418 nvmem-cells = <&boot_mode>, <&fwu_info>, <&stop2_entrypoint>; 419 nvmem-cell-names = "boot-mode", "fwu-info", "stop2-entrypoint"; 420 }; 421 }; 422 423 ddr: ddr@48040000 { 424 compatible = "st,stm32mp2-ddr"; 425 reg = <0x48040000 0x10000>, 426 <0x48c00000 0x400000>; 427 status = "okay"; 428 }; 429 430 fmc: memory-controller@48200000 { 431 #address-cells = <2>; 432 #size-cells = <1>; 433 compatible = "st,stm32mp25-fmc2-ebi"; 434 reg = <0x48200000 0x400>; 435 clocks = <&rcc CK_KER_FMC>; 436 resets = <&rcc FMC_R>; 437 status = "disabled"; 438 439 ranges = <0 0 0x70000000 0x04000000>, /* EBI CS 1 */ 440 <1 0 0x74000000 0x04000000>, /* EBI CS 2 */ 441 <2 0 0x78000000 0x04000000>, /* EBI CS 3 */ 442 <3 0 0x7c000000 0x04000000>, /* EBI CS 4 */ 443 <4 0 0x48810000 0x00001000>; /* NAND */ 444 445 nand-controller@4,0 { 446 #address-cells = <1>; 447 #size-cells = <0>; 448 compatible = "st,stm32mp25-fmc2-nfc"; 449 reg = <4 0x0000 0x10>, 450 <4 0x0090 0x10>, 451 <4 0x00a0 0x10>, 452 <4 0x0400 0x10>, 453 <4 0x0490 0x10>, 454 <4 0x04a0 0x10>, 455 <4 0x0800 0x10>, 456 <4 0x0890 0x10>, 457 <4 0x08a0 0x10>, 458 <4 0x0c00 0x10>, 459 <4 0x0c90 0x10>, 460 <4 0x0ca0 0x10>; 461 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 462 status = "disabled"; 463 }; 464 }; 465 466 /* 467 * Break node order to solve dependency probe issue between 468 * pinctrl and exti. 469 */ 470 pinctrl: pinctrl@44240000 { 471 #address-cells = <1>; 472 #size-cells = <1>; 473 compatible = "st,stm32mp257-pinctrl"; 474 ranges = <0 0x44240000 0xa0400>; 475 476 gpioa: gpio@44240000 { 477 gpio-controller; 478 #gpio-cells = <2>; 479 interrupt-controller; 480 #interrupt-cells = <2>; 481 reg = <0x0 0x400>; 482 clocks = <&rcc CK_BUS_GPIOA>; 483 st,bank-name = "GPIOA"; 484 status = "disabled"; 485 }; 486 487 gpiob: gpio@44250000 { 488 gpio-controller; 489 #gpio-cells = <2>; 490 interrupt-controller; 491 #interrupt-cells = <2>; 492 reg = <0x10000 0x400>; 493 clocks = <&rcc CK_BUS_GPIOB>; 494 st,bank-name = "GPIOB"; 495 status = "disabled"; 496 }; 497 498 gpioc: gpio@44260000 { 499 gpio-controller; 500 #gpio-cells = <2>; 501 interrupt-controller; 502 #interrupt-cells = <2>; 503 reg = <0x20000 0x400>; 504 clocks = <&rcc CK_BUS_GPIOC>; 505 st,bank-name = "GPIOC"; 506 status = "disabled"; 507 }; 508 509 gpiod: gpio@44270000 { 510 gpio-controller; 511 #gpio-cells = <2>; 512 interrupt-controller; 513 #interrupt-cells = <2>; 514 reg = <0x30000 0x400>; 515 clocks = <&rcc CK_BUS_GPIOD>; 516 st,bank-name = "GPIOD"; 517 status = "disabled"; 518 }; 519 520 gpioe: gpio@44280000 { 521 gpio-controller; 522 #gpio-cells = <2>; 523 interrupt-controller; 524 #interrupt-cells = <2>; 525 reg = <0x40000 0x400>; 526 clocks = <&rcc CK_BUS_GPIOE>; 527 st,bank-name = "GPIOE"; 528 status = "disabled"; 529 }; 530 531 gpiof: gpio@44290000 { 532 gpio-controller; 533 #gpio-cells = <2>; 534 interrupt-controller; 535 #interrupt-cells = <2>; 536 reg = <0x50000 0x400>; 537 clocks = <&rcc CK_BUS_GPIOF>; 538 st,bank-name = "GPIOF"; 539 status = "disabled"; 540 }; 541 542 gpiog: gpio@442a0000 { 543 gpio-controller; 544 #gpio-cells = <2>; 545 interrupt-controller; 546 #interrupt-cells = <2>; 547 reg = <0x60000 0x400>; 548 clocks = <&rcc CK_BUS_GPIOG>; 549 st,bank-name = "GPIOG"; 550 status = "disabled"; 551 }; 552 553 gpioh: gpio@442b0000 { 554 gpio-controller; 555 #gpio-cells = <2>; 556 interrupt-controller; 557 #interrupt-cells = <2>; 558 reg = <0x70000 0x400>; 559 clocks = <&rcc CK_BUS_GPIOH>; 560 st,bank-name = "GPIOH"; 561 status = "disabled"; 562 }; 563 564 gpioi: gpio@442c0000 { 565 gpio-controller; 566 #gpio-cells = <2>; 567 interrupt-controller; 568 #interrupt-cells = <2>; 569 reg = <0x80000 0x400>; 570 clocks = <&rcc CK_BUS_GPIOI>; 571 st,bank-name = "GPIOI"; 572 status = "disabled"; 573 }; 574 575 gpioj: gpio@442d0000 { 576 gpio-controller; 577 #gpio-cells = <2>; 578 interrupt-controller; 579 #interrupt-cells = <2>; 580 reg = <0x90000 0x400>; 581 clocks = <&rcc CK_BUS_GPIOJ>; 582 st,bank-name = "GPIOJ"; 583 status = "disabled"; 584 }; 585 586 gpiok: gpio@442e0000 { 587 gpio-controller; 588 #gpio-cells = <2>; 589 interrupt-controller; 590 #interrupt-cells = <2>; 591 reg = <0xa0000 0x400>; 592 clocks = <&rcc CK_BUS_GPIOK>; 593 st,bank-name = "GPIOK"; 594 status = "disabled"; 595 }; 596 }; 597 598 pinctrl_z: pinctrl@46200000 { 599 #address-cells = <1>; 600 #size-cells = <1>; 601 compatible = "st,stm32mp257-z-pinctrl"; 602 ranges = <0 0x46200000 0x400>; 603 604 gpioz: gpio@46200000 { 605 gpio-controller; 606 #gpio-cells = <2>; 607 interrupt-controller; 608 #interrupt-cells = <2>; 609 reg = <0 0x400>; 610 clocks = <&rcc CK_BUS_GPIOZ>; 611 st,bank-name = "GPIOZ"; 612 st,bank-ioport = <11>; 613 status = "disabled"; 614 }; 615 616 }; 617 }; 618}; 619