106e55dc8SNicolas Le Bayon /* 2066a5958SYann Gautier * Copyright (C) 2022-2024, STMicroelectronics - All Rights Reserved 306e55dc8SNicolas Le Bayon * 406e55dc8SNicolas Le Bayon * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 506e55dc8SNicolas Le Bayon */ 606e55dc8SNicolas Le Bayon 706e55dc8SNicolas Le Bayon #ifndef STM32MP_DDR_H 806e55dc8SNicolas Le Bayon #define STM32MP_DDR_H 906e55dc8SNicolas Le Bayon 1006e55dc8SNicolas Le Bayon #include <platform_def.h> 1106e55dc8SNicolas Le Bayon 1206e55dc8SNicolas Le Bayon enum stm32mp_ddr_base_type { 1306e55dc8SNicolas Le Bayon DDR_BASE, 1406e55dc8SNicolas Le Bayon DDRPHY_BASE, 1506e55dc8SNicolas Le Bayon NONE_BASE 1606e55dc8SNicolas Le Bayon }; 1706e55dc8SNicolas Le Bayon 1806e55dc8SNicolas Le Bayon enum stm32mp_ddr_reg_type { 1906e55dc8SNicolas Le Bayon REG_REG, 2006e55dc8SNicolas Le Bayon REG_TIMING, 2106e55dc8SNicolas Le Bayon REG_PERF, 2206e55dc8SNicolas Le Bayon REG_MAP, 2306e55dc8SNicolas Le Bayon REGPHY_REG, 2406e55dc8SNicolas Le Bayon REGPHY_TIMING, 2506e55dc8SNicolas Le Bayon REG_TYPE_NB 2606e55dc8SNicolas Le Bayon }; 2706e55dc8SNicolas Le Bayon 2806e55dc8SNicolas Le Bayon struct stm32mp_ddr_reg_desc { 2906e55dc8SNicolas Le Bayon uint16_t offset; /* Offset for base address */ 3006e55dc8SNicolas Le Bayon uint8_t par_offset; /* Offset for parameter array */ 31*701178dcSMaxime Méré #ifdef STM32MP2X 3279629b1aSNicolas Le Bayon bool qd; /* quasi-dynamic register if true */ 3379629b1aSNicolas Le Bayon #endif 3406e55dc8SNicolas Le Bayon }; 3506e55dc8SNicolas Le Bayon 3606e55dc8SNicolas Le Bayon struct stm32mp_ddr_reg_info { 3706e55dc8SNicolas Le Bayon const char *name; 3806e55dc8SNicolas Le Bayon const struct stm32mp_ddr_reg_desc *desc; 3906e55dc8SNicolas Le Bayon uint8_t size; 4006e55dc8SNicolas Le Bayon enum stm32mp_ddr_base_type base; 4106e55dc8SNicolas Le Bayon }; 4206e55dc8SNicolas Le Bayon 4306e55dc8SNicolas Le Bayon struct stm32mp_ddr_size { 4406e55dc8SNicolas Le Bayon uint64_t base; 4506e55dc8SNicolas Le Bayon uint64_t size; 4606e55dc8SNicolas Le Bayon }; 4706e55dc8SNicolas Le Bayon 4806e55dc8SNicolas Le Bayon struct stm32mp_ddr_priv { 4906e55dc8SNicolas Le Bayon struct stm32mp_ddr_size info; 5006e55dc8SNicolas Le Bayon struct stm32mp_ddrctl *ctl; 5106e55dc8SNicolas Le Bayon struct stm32mp_ddrphy *phy; 5206e55dc8SNicolas Le Bayon uintptr_t pwr; 5306e55dc8SNicolas Le Bayon uintptr_t rcc; 5406e55dc8SNicolas Le Bayon }; 5506e55dc8SNicolas Le Bayon 5606e55dc8SNicolas Le Bayon struct stm32mp_ddr_info { 5706e55dc8SNicolas Le Bayon const char *name; 58b4e1e8fbSYann Gautier uint32_t speed; /* in kHz */ 59b4e1e8fbSYann Gautier size_t size; /* Memory size in byte = col * row * width */ 6006e55dc8SNicolas Le Bayon }; 6106e55dc8SNicolas Le Bayon 62066a5958SYann Gautier #define DDR_DELAY_1US 1U 63066a5958SYann Gautier #define DDR_DELAY_2US 2U 64066a5958SYann Gautier #define DDR_DELAY_10US 10U 65066a5958SYann Gautier #define DDR_DELAY_50US 50U 66066a5958SYann Gautier #define DDR_TIMEOUT_500US 500U 67066a5958SYann Gautier #define DDR_TIMEOUT_US_1S 1000000U 6806e55dc8SNicolas Le Bayon 6906e55dc8SNicolas Le Bayon void stm32mp_ddr_set_reg(const struct stm32mp_ddr_priv *priv, enum stm32mp_ddr_reg_type type, 7006e55dc8SNicolas Le Bayon const void *param, const struct stm32mp_ddr_reg_info *ddr_registers); 7106e55dc8SNicolas Le Bayon void stm32mp_ddr_start_sw_done(struct stm32mp_ddrctl *ctl); 7206e55dc8SNicolas Le Bayon void stm32mp_ddr_wait_sw_done_ack(struct stm32mp_ddrctl *ctl); 7306e55dc8SNicolas Le Bayon void stm32mp_ddr_enable_axi_port(struct stm32mp_ddrctl *ctl); 74d596023bSNicolas Le Bayon int stm32mp_ddr_disable_axi_port(struct stm32mp_ddrctl *ctl); 75d596023bSNicolas Le Bayon void stm32mp_ddr_enable_host_interface(struct stm32mp_ddrctl *ctl); 76d596023bSNicolas Le Bayon void stm32mp_ddr_disable_host_interface(struct stm32mp_ddrctl *ctl); 77d596023bSNicolas Le Bayon int stm32mp_ddr_sw_selfref_entry(struct stm32mp_ddrctl *ctl); 78d596023bSNicolas Le Bayon void stm32mp_ddr_sw_selfref_exit(struct stm32mp_ddrctl *ctl); 79d596023bSNicolas Le Bayon void stm32mp_ddr_set_qd3_update_conditions(struct stm32mp_ddrctl *ctl); 80d596023bSNicolas Le Bayon void stm32mp_ddr_unset_qd3_update_conditions(struct stm32mp_ddrctl *ctl); 81d596023bSNicolas Le Bayon void stm32mp_ddr_wait_refresh_update_done_ack(struct stm32mp_ddrctl *ctl); 8206e55dc8SNicolas Le Bayon int stm32mp_board_ddr_power_init(enum ddr_type ddr_type); 8306e55dc8SNicolas Le Bayon 8406e55dc8SNicolas Le Bayon #endif /* STM32MP_DDR_H */ 85