1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2/* 3 * Copyright (c) 2026, STMicroelectronics - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. 5 */ 6#include <dt-bindings/clock/st,stm32mp21-rcc.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/reset/st,stm32mp21-rcc.h> 9 10/ { 11 #address-cells = <2>; 12 #size-cells = <2>; 13 14 cpus { 15 #address-cells = <1>; 16 #size-cells = <0>; 17 18 cpu0: cpu@0 { 19 compatible = "arm,cortex-a35"; 20 device_type = "cpu"; 21 reg = <0>; 22 enable-method = "psci"; 23 }; 24 25 domain-idle-states { 26 domain-stop1 { 27 compatible = "domain-idle-state"; 28 arm,psci-suspend-param = <0x00000011>; 29 }; 30 31 domain-lp-stop1 { 32 compatible = "domain-idle-state"; 33 arm,psci-suspend-param = <0x00000021>; 34 }; 35 36 domain-lplv-stop1 { 37 compatible = "domain-idle-state"; 38 arm,psci-suspend-param = <0x00000211>; 39 }; 40 41 domain-stop2 { 42 compatible = "domain-idle-state"; 43 arm,psci-suspend-param = <0x40001333>; 44 }; 45 46 domain-lp-stop2 { 47 compatible = "domain-idle-state"; 48 arm,psci-suspend-param = <0x40002333>; 49 }; 50 51 domain-lplv-stop2 { 52 compatible = "domain-idle-state"; 53 arm,psci-suspend-param = <0x40023333>; 54 }; 55 56 domain-standby { 57 compatible = "domain-idle-state"; 58 arm,psci-suspend-param = <0x40033333>; 59 }; 60 }; 61 }; 62 63 intc: interrupt-controller@4ac00000 { 64 compatible = "arm,cortex-a7-gic"; 65 #interrupt-cells = <3>; 66 interrupt-controller; 67 reg = <0x0 0x4ac10000 0x0 0x1000>, 68 <0x0 0x4ac20000 0x0 0x2000>, 69 <0x0 0x4ac40000 0x0 0x2000>, 70 <0x0 0x4ac60000 0x0 0x2000>; 71 }; 72 73 timer: timer { 74 compatible = "arm,armv8-timer"; 75 interrupt-parent = <&intc>; 76 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 77 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 78 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 79 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 80 always-on; 81 }; 82 83 clocks { 84 clk_hse: clk-hse { 85 #clock-cells = <0>; 86 compatible = "fixed-clock"; 87 clock-frequency = <48000000>; 88 }; 89 90 clk_hsi: clk-hsi { 91 #clock-cells = <0>; 92 compatible = "fixed-clock"; 93 clock-frequency = <64000000>; 94 }; 95 96 clk_lse: clk-lse { 97 #clock-cells = <0>; 98 compatible = "fixed-clock"; 99 clock-frequency = <32768>; 100 }; 101 102 clk_lsi: clk-lsi { 103 #clock-cells = <0>; 104 compatible = "fixed-clock"; 105 clock-frequency = <32000>; 106 }; 107 108 clk_msi: clk-msi { 109 #clock-cells = <0>; 110 compatible = "fixed-clock"; 111 clock-frequency = <16000000>; 112 }; 113 }; 114 115 soc@0 { 116 compatible = "simple-bus"; 117 #address-cells = <1>; 118 #size-cells = <1>; 119 interrupt-parent = <&intc>; 120 ranges = <0x0 0x0 0x0 0x80000000>; 121 122 rifsc: bus@42080000 { 123 compatible = "st,stm32mp25-rifsc", "simple-bus"; 124 reg = <0x42080000 0x1000>; 125 #address-cells = <1>; 126 #size-cells = <1>; 127 128 usart2: serial@400e0000 { 129 compatible = "st,stm32h7-uart"; 130 reg = <0x400e0000 0x400>; 131 clocks = <&rcc CK_KER_USART2>; 132 resets = <&rcc USART2_R>; 133 status = "disabled"; 134 }; 135 136 usart3: serial@400f0000 { 137 compatible = "st,stm32h7-uart"; 138 reg = <0x400f0000 0x400>; 139 clocks = <&rcc CK_KER_USART3>; 140 resets = <&rcc USART3_R>; 141 status = "disabled"; 142 }; 143 144 uart4: serial@40100000 { 145 compatible = "st,stm32h7-uart"; 146 reg = <0x40100000 0x400>; 147 clocks = <&rcc CK_KER_UART4>; 148 resets = <&rcc UART4_R>; 149 status = "disabled"; 150 }; 151 152 uart5: serial@40110000 { 153 compatible = "st,stm32h7-uart"; 154 reg = <0x40110000 0x400>; 155 clocks = <&rcc CK_KER_UART5>; 156 resets = <&rcc UART5_R>; 157 status = "disabled"; 158 }; 159 160 i2c1: i2c@40170000 { 161 compatible = "st,stm32mp25-i2c"; 162 reg = <0x40170000 0x400>; 163 clocks = <&rcc CK_KER_I2C1>; 164 resets = <&rcc I2C1_R>; 165 status = "disabled"; 166 }; 167 168 i2c2: i2c@40180000 { 169 compatible = "st,stm32mp25-i2c"; 170 reg = <0x40180000 0x400>; 171 clocks = <&rcc CK_KER_I2C2>; 172 resets = <&rcc I2C2_R>; 173 status = "disabled"; 174 }; 175 176 usart6: serial@40220000 { 177 compatible = "st,stm32h7-uart"; 178 reg = <0x40220000 0x400>; 179 clocks = <&rcc CK_KER_USART6>; 180 resets = <&rcc USART6_R>; 181 status = "disabled"; 182 }; 183 184 usart1: serial@40330000 { 185 compatible = "st,stm32h7-uart"; 186 reg = <0x40330000 0x400>; 187 clocks = <&rcc CK_KER_USART1>; 188 resets = <&rcc USART1_R>; 189 status = "disabled"; 190 }; 191 192 uart7: serial@40370000 { 193 compatible = "st,stm32h7-uart"; 194 reg = <0x40370000 0x400>; 195 clocks = <&rcc CK_KER_UART7>; 196 resets = <&rcc UART7_R>; 197 status = "disabled"; 198 }; 199 200 hash1: hash@42030400 { 201 compatible = "st,stm32mp13-hash"; 202 reg = <0x42030400 0x400>; 203 clocks = <&rcc CK_BUS_HASH1>; 204 resets = <&rcc HASH1_R>; 205 status = "disabled"; 206 }; 207 208 ospi1: spi@40430000 { 209 compatible = "st,stm32mp25-omi"; 210 reg = <0x40430000 0x400>; 211 clocks = <&rcc CK_KER_OSPI1>; 212 resets = <&rcc OSPI1_R>, <&rcc OSPI1DLL_R>; 213 status = "disabled"; 214 }; 215 216 rng2: rng@42020000 { 217 compatible = "st,stm32mp13-rng"; 218 reg = <0x42020000 0x400>; 219 clocks = <&rcc CK_BUS_RNG2>; 220 resets = <&rcc RNG2_R>; 221 status = "disabled"; 222 }; 223 224 rng1: rng@42030800 { 225 compatible = "st,stm32mp13-rng"; 226 reg = <0x42030800 0x400>; 227 clocks = <&rcc CK_BUS_RNG1>; 228 resets = <&rcc RNG1_R>; 229 status = "disabled"; 230 }; 231 232 iwdg1: watchdog@44010000 { 233 compatible = "st,stm32mp1-iwdg"; 234 reg = <0x44010000 0x400>; 235 clocks = <&rcc CK_BUS_IWDG1>, <&rcc LSI_CK>; 236 clock-names = "pclk", "lsi"; 237 status = "disabled"; 238 }; 239 240 i2c3: i2c@46040000 { 241 compatible = "st,stm32mp25-i2c"; 242 reg = <0x46040000 0x400>; 243 clocks = <&rcc CK_KER_I2C3>; 244 resets = <&rcc I2C3_R>; 245 status = "disabled"; 246 }; 247 248 sdmmc1: mmc@48220000 { 249 compatible = "st,stm32mp25-sdmmc2", "arm,pl18x", "arm,primecell"; 250 arm,primecell-periphid = <0x00353180>; 251 reg = <0x48220000 0x400>, <0x44230400 0x8>; 252 clocks = <&rcc CK_KER_SDMMC1>; 253 clock-names = "apb_pclk"; 254 resets = <&rcc SDMMC1_R>; 255 cap-sd-highspeed; 256 cap-mmc-highspeed; 257 max-frequency = <166000000>; 258 status = "disabled"; 259 }; 260 261 sdmmc2: mmc@48230000 { 262 compatible = "st,stm32mp25-sdmmc2", "arm,pl18x", "arm,primecell"; 263 arm,primecell-periphid = <0x00353180>; 264 reg = <0x48230000 0x400>, <0x44230800 0x8>; 265 clocks = <&rcc CK_KER_SDMMC2>; 266 clock-names = "apb_pclk"; 267 resets = <&rcc SDMMC2_R>; 268 cap-sd-highspeed; 269 cap-mmc-highspeed; 270 max-frequency = <166000000>; 271 status = "disabled"; 272 }; 273 }; 274 275 risaf2: risaf@420b0000 { 276 compatible = "st,stm32-risaf"; 277 reg = <0x420b0000 0x1000>; 278 clocks = <&rcc CK_KER_OSPI1>; 279 status = "disabled"; 280 }; 281 282 risaf4: risaf@420d0000 { 283 compatible = "st,stm32-risaf"; 284 reg = <0x420d0000 0x1000>; 285 clocks = <&rcc CK_BUS_RISAF4>; 286 status = "disabled"; 287 }; 288 289 bsec: efuse@44000000 { 290 compatible = "st,stm32mp25-bsec"; 291 reg = <0x44000000 0x1000>; 292 #address-cells = <1>; 293 #size-cells = <1>; 294 295 uid_otp: uid-otp@14 { 296 reg = <0x14 0xc>; 297 }; 298 part_number_otp: part-number-otp@24 { 299 reg = <0x24 0x4>; 300 }; 301 nand_otp: otp16@40 { 302 reg = <0x40 0x4>; 303 }; 304 lifecycle2_otp: otp18@48 { 305 reg = <0x48 0x4>; 306 }; 307 nand2_otp: otp20@50 { 308 reg = <0x50 0x4>; 309 }; 310 rev_otp@198 { 311 reg = <0x198 0x4>; 312 }; 313 package_otp: package-otp@1e8 { 314 reg = <0x1e8 0x1>; 315 }; 316 hconf1_otp: otp124@1f0 { 317 reg = <0x1f0 0x4>; 318 }; 319 pkh_otp: otp152@260 { 320 reg = <0x260 0x20>; 321 }; 322 oem_fip_enc_key: otp260@410 { 323 reg = <0x410 0x20>; 324 }; 325 }; 326 327 rcc: clock-controller@44200000 { 328 compatible = "st,stm32mp21-rcc"; 329 reg = <0x44200000 0x10000>; 330 #clock-cells = <1>; 331 #reset-cells = <1>; 332 }; 333 334 pwr: pwr@44210000 { 335 compatible = "st,stm32mp21-pwr"; 336 reg = <0x44210000 0x400>; 337 338 vddio1: vddio1 { 339 regulator-name = "vddio1"; 340 }; 341 342 vddio2: vddio2 { 343 regulator-name = "vddio2"; 344 }; 345 346 vddio3: vddio3 { 347 regulator-name = "vddio3"; 348 }; 349 350 vddio: vddio { 351 regulator-name = "vddio"; 352 }; 353 }; 354 355 syscfg: syscon@44230000 { 356 compatible = "st,stm32mp25-syscfg", "syscon"; 357 reg = <0x44230000 0x10000>; 358 }; 359 360 tamp: tamp@46010000 { 361 compatible = "st,stm32mp25-tamp"; 362 reg = <0x46010000 0x400>; 363 clocks = <&rcc CK_BUS_RTC>; 364 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 365 #address-cells = <1>; 366 #size-cells = <1>; 367 ranges; 368 369 nvram: nvram@46010100 { 370 compatible = "st,stm32mp25-tamp-nvram"; 371 #address-cells = <1>; 372 #size-cells = <1>; 373 reg = <0x46010100 0x200>; 374 375 stop2_entrypoint: tamp-bkp@2c { 376 reg = <0x2c 0x4>; 377 }; 378 fwu_info: tamp-bkp@c0 { 379 /* see firmware update info feature */ 380 reg = <0xc0 0x4>; 381 }; 382 boot_mode: tamp-bkp@180 { 383 reg = <0x180 0x4>; 384 }; 385 386 }; 387 388 boot_info: boot-info { 389 compatible = "st,stm32mp-bootinfo"; 390 nvmem-cells = <&boot_mode>, <&fwu_info>, <&stop2_entrypoint>; 391 nvmem-cell-names = "boot-mode", "fwu-info", "stop2-entrypoint"; 392 }; 393 }; 394 395 ddr: ddr@48040000 { 396 compatible = "st,stm32mp2-ddr"; 397 reg = <0x48040000 0x10000>, 398 <0x48c00000 0x400000>; 399 status = "okay"; 400 }; 401 402 fmc: memory-controller@48200000 { 403 compatible = "st,stm32mp25-fmc2-ebi"; 404 reg = <0x48200000 0x400>; 405 ranges = <0 0 0x70000000 0x04000000>, /* EBI CS 1 */ 406 <1 0 0x74000000 0x04000000>, /* EBI CS 2 */ 407 <2 0 0x78000000 0x04000000>, /* EBI CS 3 */ 408 <3 0 0x7c000000 0x04000000>, /* EBI CS 4 */ 409 <4 0 0x48810000 0x00001000>; /* NAND */ 410 #address-cells = <2>; 411 #size-cells = <1>; 412 clocks = <&rcc CK_KER_FMC>; 413 resets = <&rcc FMC_R>; 414 status = "disabled"; 415 416 nand-controller@4,0 { 417 compatible = "st,stm32mp25-fmc2-nfc"; 418 reg = <4 0x0000 0x10>, 419 <4 0x0090 0x10>, 420 <4 0x00a0 0x10>, 421 <4 0x0400 0x10>, 422 <4 0x0490 0x10>, 423 <4 0x04a0 0x10>, 424 <4 0x0800 0x10>, 425 <4 0x0890 0x10>, 426 <4 0x08a0 0x10>, 427 <4 0x0c00 0x10>, 428 <4 0x0c90 0x10>, 429 <4 0x0ca0 0x10>; 430 #address-cells = <1>; 431 #size-cells = <0>; 432 status = "disabled"; 433 }; 434 }; 435 436 pinctrl: pinctrl@44240000 { 437 #address-cells = <1>; 438 #size-cells = <1>; 439 compatible = "st,stm32mp215-pinctrl"; 440 ranges = <0 0x44240000 0x80400>; 441 442 gpioa: gpio@44240000 { 443 gpio-controller; 444 #gpio-cells = <2>; 445 interrupt-controller; 446 #interrupt-cells = <2>; 447 reg = <0x0 0x400>; 448 clocks = <&rcc CK_BUS_GPIOA>; 449 st,bank-name = "GPIOA"; 450 status = "disabled"; 451 }; 452 453 gpiob: gpio@44250000 { 454 gpio-controller; 455 #gpio-cells = <2>; 456 interrupt-controller; 457 #interrupt-cells = <2>; 458 reg = <0x10000 0x400>; 459 clocks = <&rcc CK_BUS_GPIOB>; 460 st,bank-name = "GPIOB"; 461 status = "disabled"; 462 }; 463 464 gpioc: gpio@44260000 { 465 gpio-controller; 466 #gpio-cells = <2>; 467 interrupt-controller; 468 #interrupt-cells = <2>; 469 reg = <0x20000 0x400>; 470 clocks = <&rcc CK_BUS_GPIOC>; 471 st,bank-name = "GPIOC"; 472 status = "disabled"; 473 }; 474 475 gpiod: gpio@44270000 { 476 gpio-controller; 477 #gpio-cells = <2>; 478 interrupt-controller; 479 #interrupt-cells = <2>; 480 reg = <0x30000 0x400>; 481 clocks = <&rcc CK_BUS_GPIOD>; 482 st,bank-name = "GPIOD"; 483 status = "disabled"; 484 }; 485 486 gpioe: gpio@44280000 { 487 gpio-controller; 488 #gpio-cells = <2>; 489 interrupt-controller; 490 #interrupt-cells = <2>; 491 reg = <0x40000 0x400>; 492 clocks = <&rcc CK_BUS_GPIOE>; 493 st,bank-name = "GPIOE"; 494 status = "disabled"; 495 }; 496 497 gpiof: gpio@44290000 { 498 gpio-controller; 499 #gpio-cells = <2>; 500 interrupt-controller; 501 #interrupt-cells = <2>; 502 reg = <0x50000 0x400>; 503 clocks = <&rcc CK_BUS_GPIOF>; 504 st,bank-name = "GPIOF"; 505 status = "disabled"; 506 }; 507 508 gpiog: gpio@442a0000 { 509 gpio-controller; 510 #gpio-cells = <2>; 511 interrupt-controller; 512 #interrupt-cells = <2>; 513 reg = <0x60000 0x400>; 514 clocks = <&rcc CK_BUS_GPIOG>; 515 st,bank-name = "GPIOG"; 516 status = "disabled"; 517 }; 518 519 gpioh: gpio@442b0000 { 520 gpio-controller; 521 #gpio-cells = <2>; 522 interrupt-controller; 523 #interrupt-cells = <2>; 524 reg = <0x70000 0x400>; 525 clocks = <&rcc CK_BUS_GPIOH>; 526 st,bank-name = "GPIOH"; 527 status = "disabled"; 528 }; 529 530 gpioi: gpio@442c0000 { 531 gpio-controller; 532 #gpio-cells = <2>; 533 interrupt-controller; 534 #interrupt-cells = <2>; 535 reg = <0x80000 0x400>; 536 clocks = <&rcc CK_BUS_GPIOI>; 537 st,bank-name = "GPIOI"; 538 status = "disabled"; 539 }; 540 }; 541 542 pinctrl_z: pinctrl@46200000 { 543 #address-cells = <1>; 544 #size-cells = <1>; 545 compatible = "st,stm32mp215-z-pinctrl"; 546 ranges = <0 0x46200000 0x400>; 547 548 gpioz: gpio@46200000 { 549 gpio-controller; 550 #gpio-cells = <2>; 551 interrupt-controller; 552 #interrupt-cells = <2>; 553 reg = <0 0x400>; 554 clocks = <&rcc CK_BUS_GPIOZ>; 555 st,bank-name = "GPIOZ"; 556 st,bank-ioport = <11>; 557 status = "disabled"; 558 }; 559 }; 560 }; 561}; 562