1*b4cf4102SNicolas Le Bayon// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2*b4cf4102SNicolas Le Bayon/* 3*b4cf4102SNicolas Le Bayon * Copyright (c) 2026, STMicroelectronics - All Rights Reserved 4*b4cf4102SNicolas Le Bayon * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. 5*b4cf4102SNicolas Le Bayon */ 6*b4cf4102SNicolas Le Bayon 7*b4cf4102SNicolas Le Bayon/ { 8*b4cf4102SNicolas Le Bayon soc@0 { 9*b4cf4102SNicolas Le Bayon cryp1: cryp@42030000 { 10*b4cf4102SNicolas Le Bayon compatible = "st,stm32mp1-cryp"; 11*b4cf4102SNicolas Le Bayon reg = <0x42030000 0x400>; 12*b4cf4102SNicolas Le Bayon clocks = <&rcc CK_BUS_CRYP1>; 13*b4cf4102SNicolas Le Bayon resets = <&rcc CRYP1_R>; 14*b4cf4102SNicolas Le Bayon status = "disabled"; 15*b4cf4102SNicolas Le Bayon }; 16*b4cf4102SNicolas Le Bayon 17*b4cf4102SNicolas Le Bayon cryp2: cryp@42040000 { 18*b4cf4102SNicolas Le Bayon compatible = "st,stm32mp1-cryp"; 19*b4cf4102SNicolas Le Bayon reg = <0x42040000 0x400>; 20*b4cf4102SNicolas Le Bayon clocks = <&rcc CK_BUS_CRYP2>; 21*b4cf4102SNicolas Le Bayon resets = <&rcc CRYP2_R>; 22*b4cf4102SNicolas Le Bayon status = "disabled"; 23*b4cf4102SNicolas Le Bayon }; 24*b4cf4102SNicolas Le Bayon 25*b4cf4102SNicolas Le Bayon saes: saes@42030c00 { 26*b4cf4102SNicolas Le Bayon compatible = "st,stm32-saes"; 27*b4cf4102SNicolas Le Bayon reg = <0x42030c00 0x400>; 28*b4cf4102SNicolas Le Bayon clocks = <&rcc CK_BUS_SAES>; 29*b4cf4102SNicolas Le Bayon resets = <&rcc SAES_R>; 30*b4cf4102SNicolas Le Bayon status = "disabled"; 31*b4cf4102SNicolas Le Bayon }; 32*b4cf4102SNicolas Le Bayon 33*b4cf4102SNicolas Le Bayon pka: pka@42032000 { 34*b4cf4102SNicolas Le Bayon compatible = "st,stm32mp13-pka64"; 35*b4cf4102SNicolas Le Bayon reg = <0x42032000 0x2000>; 36*b4cf4102SNicolas Le Bayon clocks = <&rcc CK_BUS_PKA>; 37*b4cf4102SNicolas Le Bayon resets = <&rcc PKA_R>; 38*b4cf4102SNicolas Le Bayon status = "disabled"; 39*b4cf4102SNicolas Le Bayon }; 40*b4cf4102SNicolas Le Bayon }; 41*b4cf4102SNicolas Le Bayon}; 42