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Searched refs:GPLL_HZ (Results 1 – 25 of 35) sorted by relevance

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/OK3568_Linux_fs/u-boot/drivers/clk/rockchip/
H A Dclk_rk3399.c56 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 3, 1);
618 return DIV_TO_RATE(GPLL_HZ, div); in rk3399_i2c_get_clk()
626 src_clk_div = GPLL_HZ / hz; in rk3399_i2c_set_clk()
717 return DIV_TO_RATE(GPLL_HZ, div); in rk3399_spi_get_clk()
725 src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1; in rk3399_spi_set_clk()
769 div = GPLL_HZ / aclk_vop; in rk3399_vop_set_clk()
823 return DIV_TO_RATE(GPLL_HZ, div); in rk3399_mmc_get_clk()
837 src_clk_div = DIV_ROUND_UP(GPLL_HZ / 2, set_rate); in rk3399_mmc_set_clk()
856 src_clk_div = DIV_ROUND_UP(GPLL_HZ , aclk_emmc); in rk3399_mmc_set_clk()
865 src_clk_div = DIV_ROUND_UP(GPLL_HZ, set_rate); in rk3399_mmc_set_clk()
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H A Dclk_rv1108.c41 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
222 return DIV_TO_RATE(GPLL_HZ, div); in rv1108_aclk_vio1_get_clk()
229 src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1; in rv1108_aclk_vio1_set_clk()
248 return DIV_TO_RATE(GPLL_HZ, div); in rv1108_aclk_vio0_get_clk()
255 src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1; in rv1108_aclk_vio0_set_clk()
283 return DIV_TO_RATE(GPLL_HZ, div); in rv1108_dclk_vop_get_clk()
290 src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1; in rv1108_dclk_vop_set_clk()
443 return DIV_TO_RATE(GPLL_HZ, div); in rv1108_i2c_get_clk()
451 src_clk_div = GPLL_HZ / hz; in rv1108_i2c_set_clk()
523 mmc_clk = DIV_TO_RATE(GPLL_HZ, div) / 2; in rv1108_mmc_get_clk()
H A Dclk_rk3036.c60 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
144 aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1; in rkclk_init()
145 assert((aclk_div + 1) * BUS_ACLK_HZ <= GPLL_HZ && aclk_div <= 0x1f); in rkclk_init()
167 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; in rkclk_init()
168 assert((aclk_div + 1) * PERI_ACLK_HZ <= GPLL_HZ && aclk_div < 0x1f); in rkclk_init()
186 nandc_div = DIV_ROUND_UP(GPLL_HZ, 150 * 1000000); in rkclk_init()
H A Dclk_rk3066.c103 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
413 aclk_div = RATE_TO_DIV(GPLL_HZ, CPU_ACLK_HZ); in rkclk_init()
414 assert((aclk_div + 1) * CPU_ACLK_HZ <= GPLL_HZ && aclk_div < 0x1f); in rkclk_init()
441 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; in rkclk_init()
442 assert((aclk_div + 1) * PERI_ACLK_HZ <= GPLL_HZ && aclk_div < 0x1f); in rkclk_init()
H A Dclk_rk3188.c101 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
443 aclk_div = DIV_ROUND_UP(GPLL_HZ, CPU_ACLK_HZ) - 1; in rkclk_init()
444 assert((aclk_div + 1) * CPU_ACLK_HZ <= GPLL_HZ && aclk_div <= 0x1f); in rkclk_init()
471 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; in rkclk_init()
472 assert((aclk_div + 1) * PERI_ACLK_HZ <= GPLL_HZ && aclk_div < 0x1f); in rkclk_init()
H A Dclk_rk3128.c436 src_clk_div = GPLL_HZ / hz; in rk3128_vop_set_clk()
480 parent = GPLL_HZ; in rk3128_vop_get_rate()
485 parent = GPLL_HZ; in rk3128_vop_get_rate()
819 priv->cru, GPLL, GPLL_HZ); in rkclk_init()
820 priv->gpll_hz = GPLL_HZ; in rkclk_init()
H A Dclk_rk3368.c58 #define GPLL_HZ (576 * 1000 * 1000) macro
116 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 2);
347 { .mux = MMC_PLL_SEL_GPLL, .rate = GPLL_HZ }, in rk3368_mmc_find_best_rate_and_parent()
466 pll_rate = GPLL_HZ; in rk3368_gmac_set_clk()
533 return DIV_TO_RATE(GPLL_HZ, div); in rk3368_spi_get_clk()
541 src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz); in rk3368_spi_set_clk()
833 parent = GPLL_HZ; in rk3368_alive_get_clk()
H A Dclk_rk3288.c220 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 4);
454 pll_rate = GPLL_HZ; in rockchip_mac_set_clk()
613 aclk_div = GPLL_HZ / PD_BUS_ACLK_HZ - 1; in rkclk_init()
614 assert((aclk_div + 1) * PD_BUS_ACLK_HZ <= GPLL_HZ && aclk_div <= 0x1f); in rkclk_init()
635 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; in rkclk_init()
636 assert((aclk_div + 1) * PERI_ACLK_HZ <= GPLL_HZ && aclk_div <= 0x1f); in rkclk_init()
H A Dclk_rv1106.c1284 if (priv->gpll_hz != GPLL_HZ) { in rv1106_clk_init()
1286 GPLL, GPLL_HZ); in rv1106_clk_init()
1288 priv->gpll_hz = GPLL_HZ; in rv1106_clk_init()
1308 priv->gpll_hz = GPLL_HZ; in rv1106_clk_probe()
H A Dclk_rk3328.c289 pll_rate = GPLL_HZ; in rk3328_gmac2phy_src_set_clk()
1301 priv->cru, GPLL, GPLL_HZ); in rkclk_init()
1302 priv->gpll_hz = GPLL_HZ; in rkclk_init()
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dcru_rk3188.h13 #define GPLL_HZ (594 * 1000000) macro
H A Dcru_rk3066.h13 #define GPLL_HZ (594 * 1000000) macro
H A Dcru_rk3399.h82 #define GPLL_HZ (800 * MHz) macro
H A Dcru_rk3128.h16 #define GPLL_HZ (594 * MHz) macro
H A Dcru_rk3036.h14 #define GPLL_HZ (594 * 1000000) macro
H A Dcru_rk322x.h14 #define GPLL_HZ (1200 * MHz) macro
H A Dcru_rv1108.h15 #define GPLL_HZ (1188 * 1000000) macro
H A Dcru_rk3288.h15 #define GPLL_HZ (594 * 1000000) macro
H A Dcru_rk3328.h75 #define GPLL_HZ 491520000 macro
H A Dcru_rv1106.h21 #define GPLL_HZ (1188 * MHz) macro
H A Dcru_rk1808.h16 #define GPLL_HZ (594 * MHz) macro
H A Dcru_rk3528.h16 #define GPLL_HZ (1188 * MHz) macro
H A Dcru_rv1126.h21 #define GPLL_HZ (1188 * MHz) macro
H A Dcru_px30.h16 #define GPLL_HZ (1200 * MHz) macro
H A Dcru_rk3562.h18 #define GPLL_HZ (1188 * MHz) macro

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