Lines Matching refs:GPLL_HZ
56 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 3, 1);
618 return DIV_TO_RATE(GPLL_HZ, div); in rk3399_i2c_get_clk()
626 src_clk_div = GPLL_HZ / hz; in rk3399_i2c_set_clk()
717 return DIV_TO_RATE(GPLL_HZ, div); in rk3399_spi_get_clk()
725 src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1; in rk3399_spi_set_clk()
769 div = GPLL_HZ / aclk_vop; in rk3399_vop_set_clk()
823 return DIV_TO_RATE(GPLL_HZ, div); in rk3399_mmc_get_clk()
837 src_clk_div = DIV_ROUND_UP(GPLL_HZ / 2, set_rate); in rk3399_mmc_set_clk()
856 src_clk_div = DIV_ROUND_UP(GPLL_HZ , aclk_emmc); in rk3399_mmc_set_clk()
865 src_clk_div = DIV_ROUND_UP(GPLL_HZ, set_rate); in rk3399_mmc_set_clk()
1018 parent = GPLL_HZ; in rk3399_crypto_get_clk()
1023 parent = GPLL_HZ; in rk3399_crypto_get_clk()
1038 src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz); in rk3399_crypto_set_clk()
1077 parent = GPLL_HZ; in rk3399_peri_get_clk()
1095 parent = GPLL_HZ; in rk3399_peri_get_clk()
1113 parent = GPLL_HZ; in rk3399_peri_get_clk()
1136 parent = GPLL_HZ; in rk3399_alive_get_clk()
1415 if (rkclk_pll_get_rate(&cru->gpll_con[0]) == GPLL_HZ) in rkclk_init()
1423 aclk_div = DIV_ROUND_UP(GPLL_HZ, PERIHP_ACLK_HZ) - 1; in rkclk_init()
1442 aclk_div = DIV_ROUND_UP(GPLL_HZ, PERILP0_ACLK_HZ) - 1; in rkclk_init()
1461 hclk_div = DIV_ROUND_UP(GPLL_HZ, PERILP1_HCLK_HZ) - 1; in rkclk_init()
1463 GPLL_HZ && (hclk_div <= 0x1f)); in rkclk_init()