1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2016 Rockchip Electronics Co., Ltd 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __ASM_ARCH_CRU_RK3399_H_ 8*4882a593Smuzhiyun #define __ASM_ARCH_CRU_RK3399_H_ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <common.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* Private data for the clock driver - used by rockchip_get_cru() */ 13*4882a593Smuzhiyun struct rk3399_clk_priv { 14*4882a593Smuzhiyun struct rk3399_cru *cru; 15*4882a593Smuzhiyun ulong armlclk_hz; 16*4882a593Smuzhiyun ulong armlclk_enter_hz; 17*4882a593Smuzhiyun ulong armlclk_init_hz; 18*4882a593Smuzhiyun ulong armbclk_hz; 19*4882a593Smuzhiyun ulong armbclk_enter_hz; 20*4882a593Smuzhiyun ulong armbclk_init_hz; 21*4882a593Smuzhiyun bool sync_kernel; 22*4882a593Smuzhiyun bool set_armclk_rate; 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun struct rk3399_pmuclk_priv { 26*4882a593Smuzhiyun struct rk3399_pmucru *pmucru; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun struct rk3399_pmucru { 30*4882a593Smuzhiyun u32 ppll_con[6]; 31*4882a593Smuzhiyun u32 reserved[0x1a]; 32*4882a593Smuzhiyun u32 pmucru_clksel[6]; 33*4882a593Smuzhiyun u32 pmucru_clkfrac_con[2]; 34*4882a593Smuzhiyun u32 reserved2[0x18]; 35*4882a593Smuzhiyun u32 pmucru_clkgate_con[3]; 36*4882a593Smuzhiyun u32 reserved3; 37*4882a593Smuzhiyun u32 pmucru_softrst_con[2]; 38*4882a593Smuzhiyun u32 reserved4[2]; 39*4882a593Smuzhiyun u32 pmucru_rstnhold_con[2]; 40*4882a593Smuzhiyun u32 reserved5[2]; 41*4882a593Smuzhiyun u32 pmucru_gatedis_con[2]; 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun check_member(rk3399_pmucru, pmucru_gatedis_con[1], 0x134); 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun struct rk3399_cru { 46*4882a593Smuzhiyun u32 apll_l_con[6]; 47*4882a593Smuzhiyun u32 reserved[2]; 48*4882a593Smuzhiyun u32 apll_b_con[6]; 49*4882a593Smuzhiyun u32 reserved1[2]; 50*4882a593Smuzhiyun u32 dpll_con[6]; 51*4882a593Smuzhiyun u32 reserved2[2]; 52*4882a593Smuzhiyun u32 cpll_con[6]; 53*4882a593Smuzhiyun u32 reserved3[2]; 54*4882a593Smuzhiyun u32 gpll_con[6]; 55*4882a593Smuzhiyun u32 reserved4[2]; 56*4882a593Smuzhiyun u32 npll_con[6]; 57*4882a593Smuzhiyun u32 reserved5[2]; 58*4882a593Smuzhiyun u32 vpll_con[6]; 59*4882a593Smuzhiyun u32 reserved6[0x0a]; 60*4882a593Smuzhiyun u32 clksel_con[108]; 61*4882a593Smuzhiyun u32 reserved7[0x14]; 62*4882a593Smuzhiyun u32 clkgate_con[35]; 63*4882a593Smuzhiyun u32 reserved8[0x1d]; 64*4882a593Smuzhiyun u32 softrst_con[21]; 65*4882a593Smuzhiyun u32 reserved9[0x2b]; 66*4882a593Smuzhiyun u32 glb_srst_fst_value; 67*4882a593Smuzhiyun u32 glb_srst_snd_value; 68*4882a593Smuzhiyun u32 glb_cnt_th; 69*4882a593Smuzhiyun u32 misc_con; 70*4882a593Smuzhiyun u32 glb_rst_con; 71*4882a593Smuzhiyun u32 glb_rst_st; 72*4882a593Smuzhiyun u32 reserved10[0x1a]; 73*4882a593Smuzhiyun u32 sdmmc_con[2]; 74*4882a593Smuzhiyun u32 sdio0_con[2]; 75*4882a593Smuzhiyun u32 sdio1_con[2]; 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun check_member(rk3399_cru, sdio1_con[1], 0x594); 78*4882a593Smuzhiyun #define MHz 1000000 79*4882a593Smuzhiyun #define KHz 1000 80*4882a593Smuzhiyun #define OSC_HZ (24*MHz) 81*4882a593Smuzhiyun #define APLL_HZ (600*MHz) 82*4882a593Smuzhiyun #define GPLL_HZ (800 * MHz) 83*4882a593Smuzhiyun #define CPLL_HZ (384*MHz) 84*4882a593Smuzhiyun #define NPLL_HZ (600 * MHz) 85*4882a593Smuzhiyun #define PPLL_HZ (676*MHz) 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun #define PMU_PCLK_HZ (48*MHz) 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun #define ACLKM_CORE_HZ (300*MHz) 90*4882a593Smuzhiyun #define ATCLK_CORE_HZ (300*MHz) 91*4882a593Smuzhiyun #define PCLK_DBG_HZ (100*MHz) 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun #define PERIHP_ACLK_HZ (150 * MHz) 94*4882a593Smuzhiyun #define PERIHP_HCLK_HZ (75 * MHz) 95*4882a593Smuzhiyun #define PERIHP_PCLK_HZ (37500 * KHz) 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun #define PERILP0_ACLK_HZ (300 * MHz) 98*4882a593Smuzhiyun #define PERILP0_HCLK_HZ (100 * MHz) 99*4882a593Smuzhiyun #define PERILP0_PCLK_HZ (50 * MHz) 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun #define PERILP1_HCLK_HZ (100 * MHz) 102*4882a593Smuzhiyun #define PERILP1_PCLK_HZ (50 * MHz) 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun #define PWM_CLOCK_HZ PMU_PCLK_HZ 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun enum apll_frequencies { 107*4882a593Smuzhiyun APLL_1600_MHZ, 108*4882a593Smuzhiyun APLL_816_MHZ, 109*4882a593Smuzhiyun APLL_600_MHZ, 110*4882a593Smuzhiyun }; 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun enum cpu_cluster { 113*4882a593Smuzhiyun CPU_CLUSTER_LITTLE, 114*4882a593Smuzhiyun CPU_CLUSTER_BIG, 115*4882a593Smuzhiyun }; 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun enum rk3399_pll_id { 118*4882a593Smuzhiyun APLLL_ID = 0, 119*4882a593Smuzhiyun APLLB_ID, 120*4882a593Smuzhiyun DPLL_ID, 121*4882a593Smuzhiyun CPLL_ID, 122*4882a593Smuzhiyun GPLL_ID, 123*4882a593Smuzhiyun NPLL_ID, 124*4882a593Smuzhiyun VPLL_ID, 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun PPLL_ID, 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun END_PLL_ID 129*4882a593Smuzhiyun }; 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun struct rk3399_clk_info { 132*4882a593Smuzhiyun unsigned long id; 133*4882a593Smuzhiyun char *name; 134*4882a593Smuzhiyun bool is_cru; 135*4882a593Smuzhiyun }; 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun #endif /* __ASM_ARCH_CRU_RK3399_H_ */ 138