1 /* 2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #ifndef _ASM_ARCH_CRU_px30_H 7 #define _ASM_ARCH_CRU_px30_H 8 9 #include <common.h> 10 11 #define MHz 1000000 12 #define KHz 1000 13 #define OSC_HZ (24 * MHz) 14 15 #define APLL_HZ (600 * MHz) 16 #define GPLL_HZ (1200 * MHz) 17 #define NPLL_HZ (1188 * MHz) 18 #define ACLK_BUS_HZ (200 * MHz) 19 #define HCLK_BUS_HZ (150 * MHz) 20 #define PCLK_BUS_HZ (100 * MHz) 21 #define ACLK_PERI_HZ (200 * MHz) 22 #define HCLK_PERI_HZ (150 * MHz) 23 #define PCLK_PMU_HZ (100 * MHz) 24 25 /* PX30 pll id */ 26 enum px30_pll_id { 27 APLL, 28 DPLL, 29 CPLL, 30 NPLL, 31 GPLL, 32 PLL_COUNT, 33 }; 34 35 struct px30_clk_info { 36 unsigned long id; 37 char *name; 38 bool is_cru; 39 }; 40 41 /* Private data for the clock driver - used by rockchip_get_cru() */ 42 struct px30_clk_priv { 43 struct px30_cru *cru; 44 ulong gpll_hz; 45 ulong armclk_hz; 46 ulong armclk_enter_hz; 47 ulong armclk_init_hz; 48 bool sync_kernel; 49 bool set_armclk_rate; 50 }; 51 52 struct px30_pmuclk_priv { 53 struct px30_pmucru *pmucru; 54 ulong gpll_hz; 55 }; 56 57 struct px30_pll { 58 unsigned int con0; 59 unsigned int con1; 60 unsigned int con2; 61 unsigned int con3; 62 unsigned int con4; 63 unsigned int reserved0[3]; 64 }; 65 66 struct px30_cru { 67 struct px30_pll pll[4]; 68 unsigned int reserved1[8]; 69 unsigned int mode; 70 unsigned int misc; 71 unsigned int reserved2[2]; 72 unsigned int glb_cnt_th; 73 unsigned int glb_rst_st; 74 unsigned int glb_srst_fst; 75 unsigned int glb_srst_snd; 76 unsigned int glb_rst_con; 77 unsigned int reserved3[7]; 78 unsigned int hwffc_con0; 79 unsigned int reserved4; 80 unsigned int hwffc_th; 81 unsigned int hwffc_intst; 82 unsigned int apll_con0_s; 83 unsigned int apll_con1_s; 84 unsigned int clksel_con0_s; 85 unsigned int reserved5; 86 unsigned int clksel_con[60]; 87 unsigned int reserved6[4]; 88 unsigned int clkgate_con[18]; 89 unsigned int reserved7[(0x280 - 0x244) / 4 - 1]; 90 unsigned int ssgtbl[32]; 91 unsigned int softrst_con[12]; 92 unsigned int reserved8[(0x380 - 0x32c) / 4 - 1]; 93 unsigned int sdmmc_con[2]; 94 unsigned int sdio_con[2]; 95 unsigned int emmc_con[2]; 96 unsigned int reserved9[(0x400 - 0x394) / 4 - 1]; 97 unsigned int autocs_con[8]; 98 }; 99 100 check_member(px30_cru, autocs_con[7], 0x41c); 101 102 struct px30_pmucru { 103 struct px30_pll pll; 104 unsigned int pmu_mode; 105 unsigned int reserved1[7]; 106 unsigned int pmu_clksel_con[6]; 107 unsigned int reserved2[10]; 108 unsigned int pmu_clkgate_con[2]; 109 unsigned int reserved3[14]; 110 unsigned int pmu_autocs_con[2]; 111 }; 112 113 check_member(px30_pmucru, pmu_autocs_con[1], 0xc4); 114 115 struct pll_rate_table { 116 unsigned long rate; 117 unsigned int fbdiv; 118 unsigned int postdiv1; 119 unsigned int refdiv; 120 unsigned int postdiv2; 121 unsigned int dsmpd; 122 unsigned int frac; 123 }; 124 125 struct cpu_rate_table { 126 unsigned long rate; 127 unsigned int aclk_div; 128 unsigned int pclk_div; 129 }; 130 131 enum { 132 /* PLLCON0*/ 133 PLL_BP_SHIFT = 15, 134 PLL_POSTDIV1_SHIFT = 12, 135 PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT, 136 PLL_FBDIV_SHIFT = 0, 137 PLL_FBDIV_MASK = 0xfff, 138 139 /* PLLCON1 */ 140 PLL_PDSEL_SHIFT = 15, 141 PLL_PD1_SHIFT = 14, 142 PLL_PD_SHIFT = 13, 143 PLL_PD_MASK = 1 << PLL_PD_SHIFT, 144 PLL_DSMPD_SHIFT = 12, 145 PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT, 146 PLL_LOCK_STATUS_SHIFT = 10, 147 PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT, 148 PLL_POSTDIV2_SHIFT = 6, 149 PLL_POSTDIV2_MASK = 7 << PLL_POSTDIV2_SHIFT, 150 PLL_REFDIV_SHIFT = 0, 151 PLL_REFDIV_MASK = 0x3f, 152 153 /* PLLCON2 */ 154 PLL_FOUT4PHASEPD_SHIFT = 27, 155 PLL_FOUTVCOPD_SHIFT = 26, 156 PLL_FOUTPOSTDIVPD_SHIFT = 25, 157 PLL_DACPD_SHIFT = 24, 158 PLL_FRAC_DIV = 0xffffff, 159 160 /* CRU_MODE */ 161 PLLMUX_FROM_XIN24M = 0, 162 PLLMUX_FROM_PLL, 163 PLLMUX_FROM_RTC32K, 164 USBPHY480M_MODE_SHIFT = 8, 165 USBPHY480M_MODE_MASK = 3 << USBPHY480M_MODE_SHIFT, 166 NPLL_MODE_SHIFT = 6, 167 NPLL_MODE_MASK = 3 << NPLL_MODE_SHIFT, 168 DPLL_MODE_SHIFT = 4, 169 DPLL_MODE_MASK = 3 << DPLL_MODE_SHIFT, 170 CPLL_MODE_SHIFT = 2, 171 CPLL_MODE_MASK = 3 << CPLL_MODE_SHIFT, 172 APLL_MODE_SHIFT = 0, 173 APLL_MODE_MASK = 3 << APLL_MODE_SHIFT, 174 175 /* CRU_CLK_SEL0_CON */ 176 CORE_ACLK_DIV_SHIFT = 12, 177 CORE_ACLK_DIV_MASK = 0x07 << CORE_ACLK_DIV_SHIFT, 178 CORE_DBG_DIV_SHIFT = 8, 179 CORE_DBG_DIV_MASK = 0x03 << CORE_DBG_DIV_SHIFT, 180 CORE_CLK_PLL_SEL_SHIFT = 7, 181 CORE_CLK_PLL_SEL_MASK = 1 << CORE_CLK_PLL_SEL_SHIFT, 182 CORE_CLK_PLL_SEL_APLL = 0, 183 CORE_CLK_PLL_SEL_GPLL, 184 CORE_DIV_CON_SHIFT = 0, 185 CORE_DIV_CON_MASK = 0x0f << CORE_DIV_CON_SHIFT, 186 187 /* CRU_CLK_SEL3_CON */ 188 ACLK_VO_PLL_SHIFT = 6, 189 ACLK_VO_PLL_MASK = 0x3 << ACLK_VO_PLL_SHIFT, 190 ACLK_VO_SEL_GPLL = 0, 191 ACLK_VO_SEL_CPLL, 192 ACLK_VO_SEL_NPLL, 193 ACLK_VO_DIV_SHIFT = 0, 194 ACLK_VO_DIV_MASK = 0x1f << ACLK_VO_DIV_SHIFT, 195 196 /* CRU_CLK_SEL5_CON */ 197 DCLK_VOPB_SEL_SHIFT = 14, 198 DCLK_VOPB_SEL_MASK = 0x3 << DCLK_VOPB_SEL_SHIFT, 199 DCLK_VOPB_SEL_DIVOUT = 0, 200 DCLK_VOPB_SEL_FRACOUT, 201 DCLK_VOPB_SEL_24M, 202 DCLK_VOPB_PLL_SEL_SHIFT = 11, 203 DCLK_VOPB_PLL_SEL_MASK = 0x1 << DCLK_VOPB_PLL_SEL_SHIFT, 204 DCLK_VOPB_PLL_SEL_CPLL = 0, 205 DCLK_VOPB_PLL_SEL_NPLL, 206 DCLK_VOPB_DIV_SHIFT = 0, 207 DCLK_VOPB_DIV_MASK = 0xff, 208 209 /* CRU_CLK_SEL8_CON */ 210 DCLK_VOPL_SEL_SHIFT = 14, 211 DCLK_VOPL_SEL_MASK = 0x3 << DCLK_VOPL_SEL_SHIFT, 212 DCLK_VOPL_SEL_DIVOUT = 0, 213 DCLK_VOPL_SEL_FRACOUT, 214 DCLK_VOPL_SEL_24M, 215 DCLK_VOPL_PLL_SEL_SHIFT = 11, 216 DCLK_VOPL_PLL_SEL_MASK = 0x1 << DCLK_VOPL_PLL_SEL_SHIFT, 217 DCLK_VOPL_PLL_SEL_NPLL = 0, 218 DCLK_VOPL_PLL_SEL_CPLL, 219 DCLK_VOPL_DIV_SHIFT = 0, 220 DCLK_VOPL_DIV_MASK = 0xff, 221 222 /* CRU_CLK_SEL14_CON */ 223 PERI_PLL_SEL_SHIFT =15, 224 PERI_PLL_SEL_MASK = 3 << PERI_PLL_SEL_SHIFT, 225 PERI_PLL_GPLL = 0, 226 PERI_PLL_CPLL, 227 PERI_HCLK_DIV_SHIFT = 8, 228 PERI_HCLK_DIV_MASK = 0x1f << PERI_HCLK_DIV_SHIFT, 229 PERI_ACLK_DIV_SHIFT = 0, 230 PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT, 231 232 /* CRU_CLKSEL15_CON */ 233 NANDC_CLK_SEL_SHIFT = 15, 234 NANDC_CLK_SEL_MASK = 0x1 << NANDC_CLK_SEL_SHIFT, 235 NANDC_CLK_SEL_NANDC = 0, 236 NANDC_CLK_SEL_NANDC_DIV50, 237 NANDC_DIV50_SHIFT = 8, 238 NANDC_DIV50_MASK = 0x1f << NANDC_DIV50_SHIFT, 239 NANDC_PLL_SHIFT = 6, 240 NANDC_PLL_MASK = 0x3 << NANDC_PLL_SHIFT, 241 NANDC_SEL_GPLL = 0, 242 NANDC_SEL_CPLL, 243 NANDC_SEL_NPLL, 244 NANDC_DIV_SHIFT = 0, 245 NANDC_DIV_MASK = 0x1f << NANDC_DIV_SHIFT, 246 247 /* CRU_CLKSEL20_CON */ 248 EMMC_PLL_SHIFT = 14, 249 EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT, 250 EMMC_SEL_GPLL = 0, 251 EMMC_SEL_CPLL, 252 EMMC_SEL_NPLL, 253 EMMC_SEL_24M, 254 EMMC_DIV_SHIFT = 0, 255 EMMC_DIV_MASK = 0xff << EMMC_DIV_SHIFT, 256 257 /* CRU_CLKSEL21_CON */ 258 EMMC_CLK_SEL_SHIFT = 15, 259 EMMC_CLK_SEL_MASK = 1 << EMMC_CLK_SEL_SHIFT, 260 EMMC_CLK_SEL_EMMC = 0, 261 EMMC_CLK_SEL_EMMC_DIV50, 262 EMMC_DIV50_SHIFT = 0, 263 EMMC_DIV50_MASK = 0xff << EMMC_DIV_SHIFT, 264 265 /* CRU_CLKSEL22_CON */ 266 GMAC_PLL_SEL_SHIFT = 14, 267 GMAC_PLL_SEL_MASK = 3 << GMAC_PLL_SEL_SHIFT, 268 GMAC_PLL_SEL_GPLL = 0, 269 GMAC_PLL_SEL_CPLL, 270 GMAC_PLL_SEL_NPLL, 271 CLK_GMAC_DIV_SHIFT = 8, 272 CLK_GMAC_DIV_MASK = 0x1f << CLK_GMAC_DIV_SHIFT, 273 SFC_PLL_SEL_SHIFT = 7, 274 SFC_PLL_SEL_MASK = 1 << SFC_PLL_SEL_SHIFT, 275 SFC_DIV_CON_SHIFT = 0, 276 SFC_DIV_CON_MASK = 0x7f, 277 278 /* CRU_CLK_SEL23_CON */ 279 BUS_PLL_SEL_SHIFT =15, 280 BUS_PLL_SEL_MASK = 1 << BUS_PLL_SEL_SHIFT, 281 BUS_PLL_SEL_GPLL = 0, 282 BUS_PLL_SEL_CPLL, 283 BUS_ACLK_DIV_SHIFT = 8, 284 BUS_ACLK_DIV_MASK = 0x1f << BUS_ACLK_DIV_SHIFT, 285 RMII_CLK_SEL_SHIFT = 7, 286 RMII_CLK_SEL_MASK = 1 << RMII_CLK_SEL_SHIFT, 287 RMII_CLK_SEL_10M = 0, 288 RMII_CLK_SEL_100M, 289 RMII_EXTCLK_SEL_SHIFT = 6, 290 RMII_EXTCLK_SEL_MASK = 1 << RMII_EXTCLK_SEL_SHIFT, 291 RMII_EXTCLK_SEL_INT = 0, 292 RMII_EXTCLK_SEL_EXT, 293 PCLK_GMAC_DIV_SHIFT = 0, 294 PCLK_GMAC_DIV_MASK = 0x0f << PCLK_GMAC_DIV_SHIFT, 295 296 /* CRU_CLK_SEL24_CON */ 297 BUS_PCLK_DIV_SHIFT = 8, 298 BUS_PCLK_DIV_MASK = 3 << BUS_PCLK_DIV_SHIFT, 299 BUS_HCLK_DIV_SHIFT = 0, 300 BUS_HCLK_DIV_MASK = 0x1f << BUS_HCLK_DIV_SHIFT, 301 302 /* CRU_CLK_SEL25_CON */ 303 CRYPTO_APK_SEL_SHIFT = 14, 304 CRYPTO_APK_PLL_SEL_MASK = 3 << CRYPTO_APK_SEL_SHIFT, 305 CRYPTO_PLL_SEL_GPLL = 0, 306 CRYPTO_PLL_SEL_CPLL, 307 CRYPTO_PLL_SEL_NPLL = 0, 308 CRYPTO_APK_DIV_SHIFT = 8, 309 CRYPTO_APK_DIV_MASK = 0x1f << CRYPTO_APK_DIV_SHIFT, 310 CRYPTO_PLL_SEL_SHIFT = 6, 311 CRYPTO_PLL_SEL_MASK = 3 << CRYPTO_PLL_SEL_SHIFT, 312 CRYPTO_DIV_SHIFT = 0, 313 CRYPTO_DIV_MASK = 0x1f << CRYPTO_DIV_SHIFT, 314 315 /* CRU_CLK_SEL30_CON */ 316 CLK_I2S1_DIV_CON_MASK = 0x7f, 317 CLK_I2S1_PLL_SEL_MASK = 0X1 << 8, 318 CLK_I2S1_PLL_SEL_GPLL = 0X0 << 8, 319 CLK_I2S1_PLL_SEL_NPLL = 0X1 << 8, 320 CLK_I2S1_SEL_MASK = 0x3 << 10, 321 CLK_I2S1_SEL_I2S1 = 0x0 << 10, 322 CLK_I2S1_SEL_FRAC = 0x1 << 10, 323 CLK_I2S1_SEL_MCLK_IN = 0x2 << 10, 324 CLK_I2S1_SEL_OSC = 0x3 << 10, 325 CLK_I2S1_OUT_SEL_MASK = 0x1 << 15, 326 CLK_I2S1_OUT_SEL_I2S1 = 0x0 << 15, 327 CLK_I2S1_OUT_SEL_OSC = 0x1 << 15, 328 329 /* CRU_CLK_SEL31_CON */ 330 CLK_I2S1_FRAC_NUMERATOR_SHIFT = 16, 331 CLK_I2S1_FRAC_NUMERATOR_MASK = 0xffff << 16, 332 CLK_I2S1_FRAC_DENOMINATOR_SHIFT = 0, 333 CLK_I2S1_FRAC_DENOMINATOR_MASK = 0xffff, 334 335 /* CRU_CLK_SEL34_CON */ 336 UART1_PLL_SEL_SHIFT = 14, 337 UART1_PLL_SEL_MASK = 3 << UART1_PLL_SEL_SHIFT, 338 UART1_PLL_SEL_GPLL = 0, 339 UART1_PLL_SEL_24M, 340 UART1_PLL_SEL_480M, 341 UART1_PLL_SEL_NPLL, 342 UART1_DIV_CON_SHIFT = 0, 343 UART1_DIV_CON_MASK = 0x1f << UART1_DIV_CON_SHIFT, 344 345 /* CRU_CLK_SEL35_CON */ 346 UART1_CLK_SEL_SHIFT = 14, 347 UART1_CLK_SEL_MASK = 3 << UART1_PLL_SEL_SHIFT, 348 UART1_CLK_SEL_UART1 = 0, 349 UART1_CLK_SEL_UART1_NP5, 350 UART1_CLK_SEL_UART1_FRAC, 351 UART1_DIVNP5_SHIFT = 0, 352 UART1_DIVNP5_MASK = 0x1f << UART1_DIVNP5_SHIFT, 353 354 /* CRU_CLK_SEL37_CON */ 355 UART2_PLL_SEL_SHIFT = 14, 356 UART2_PLL_SEL_MASK = 3 << UART2_PLL_SEL_SHIFT, 357 UART2_PLL_SEL_GPLL = 0, 358 UART2_PLL_SEL_24M, 359 UART2_PLL_SEL_480M, 360 UART2_PLL_SEL_NPLL, 361 UART2_DIV_CON_SHIFT = 0, 362 UART2_DIV_CON_MASK = 0x1f << UART2_DIV_CON_SHIFT, 363 364 /* CRU_CLK_SEL38_CON */ 365 UART2_CLK_SEL_SHIFT = 14, 366 UART2_CLK_SEL_MASK = 3 << UART2_PLL_SEL_SHIFT, 367 UART2_CLK_SEL_UART2 = 0, 368 UART2_CLK_SEL_UART2_NP5, 369 UART2_CLK_SEL_UART2_FRAC, 370 UART2_DIVNP5_SHIFT = 0, 371 UART2_DIVNP5_MASK = 0x1f << UART2_DIVNP5_SHIFT, 372 373 /* CRU_CLK_SEL46_CON */ 374 UART5_PLL_SEL_SHIFT = 14, 375 UART5_PLL_SEL_MASK = 3 << UART5_PLL_SEL_SHIFT, 376 UART5_PLL_SEL_GPLL = 0, 377 UART5_PLL_SEL_24M, 378 UART5_PLL_SEL_480M, 379 UART5_PLL_SEL_NPLL, 380 UART5_DIV_CON_SHIFT = 0, 381 UART5_DIV_CON_MASK = 0x1f << UART5_DIV_CON_SHIFT, 382 383 /* CRU_CLK_SEL47_CON */ 384 UART5_CLK_SEL_SHIFT = 14, 385 UART5_CLK_SEL_MASK = 3 << UART5_PLL_SEL_SHIFT, 386 UART5_CLK_SEL_UART5 = 0, 387 UART5_CLK_SEL_UART5_NP5, 388 UART5_CLK_SEL_UART5_FRAC, 389 UART5_DIVNP5_SHIFT = 0, 390 UART5_DIVNP5_MASK = 0x1f << UART5_DIVNP5_SHIFT, 391 392 /* CRU_CLK_SEL49_CON */ 393 CLK_I2C_PLL_SEL_GPLL = 0, 394 CLK_I2C_PLL_SEL_24M, 395 CLK_I2C_DIV_CON_MASK = 0x7f, 396 CLK_I2C_PLL_SEL_MASK = 1, 397 CLK_I2C1_PLL_SEL_SHIFT = 15, 398 CLK_I2C1_DIV_CON_SHIFT = 8, 399 CLK_I2C0_PLL_SEL_SHIFT = 7, 400 CLK_I2C0_DIV_CON_SHIFT = 0, 401 402 /* CRU_CLK_SEL50_CON */ 403 CLK_I2C3_PLL_SEL_SHIFT = 15, 404 CLK_I2C3_DIV_CON_SHIFT = 8, 405 CLK_I2C2_PLL_SEL_SHIFT = 7, 406 CLK_I2C2_DIV_CON_SHIFT = 0, 407 408 /* CRU_CLK_SEL52_CON */ 409 CLK_PWM_PLL_SEL_GPLL = 0, 410 CLK_PWM_PLL_SEL_24M, 411 CLK_PWM_DIV_CON_MASK = 0x7f, 412 CLK_PWM_PLL_SEL_MASK = 1, 413 CLK_PWM1_PLL_SEL_SHIFT = 15, 414 CLK_PWM1_DIV_CON_SHIFT = 8, 415 CLK_PWM0_PLL_SEL_SHIFT = 7, 416 CLK_PWM0_DIV_CON_SHIFT = 0, 417 418 /* CRU_CLK_SEL53_CON */ 419 CLK_SPI_PLL_SEL_GPLL = 0, 420 CLK_SPI_PLL_SEL_24M, 421 CLK_SPI_DIV_CON_MASK = 0x7f, 422 CLK_SPI_PLL_SEL_MASK = 1, 423 CLK_SPI1_PLL_SEL_SHIFT = 15, 424 CLK_SPI1_DIV_CON_SHIFT = 8, 425 CLK_SPI0_PLL_SEL_SHIFT = 7, 426 CLK_SPI0_DIV_CON_SHIFT = 0, 427 428 /* CRU_CLK_SEL55_CON */ 429 CLK_SARADC_DIV_CON_SHIFT = 0, 430 CLK_SARADC_DIV_CON_MASK = 0x7ff, 431 432 /* CRU_CLK_SEL56_CON */ 433 CLK_OTP_USR_DIV_CON_SHIFT = 4, 434 CLK_OTP_USR_DIV_CON_MASK = 0x3 << CLK_OTP_USR_DIV_CON_SHIFT, 435 CLK_OTP_DIV_CON_SHIFT = 0, 436 CLK_OTP_DIV_CON_MASK = 0x7, 437 CLK_OTP_S_SEL_SHIFT = 8, 438 CLK_OTP_S_SEL_MASK = 1 << CLK_OTP_S_SEL_SHIFT, 439 CLK_OTP_S_SEL_XIN24M = 0, 440 CLK_OTP_S_SEL_GPLL, 441 CLK_OTP_S_DIV_CON_SHIFT = 0, 442 CLK_OTP_S_DIV_CON_MASK = 0x1FF, 443 444 /* CRU_CLK_GATE10_CON */ 445 CLK_I2S1_OUT_MCLK_PAD_MASK = 0x1 << 9, 446 CLK_I2S1_OUT_MCLK_PAD_ENABLE = 0x1 << 9, 447 CLK_I2S1_OUT_MCLK_PAD_DISABLE = 0x0 << 9, 448 449 /* CRU_PMU_MODE */ 450 GPLL_MODE_SHIFT = 0, 451 GPLL_MODE_MASK = 3 << GPLL_MODE_SHIFT, 452 453 /* CRU_PMU_CLK_SEL0_CON */ 454 CLK_PMU_PCLK_DIV_SHIFT = 0, 455 CLK_PMU_PCLK_DIV_MASK = 0x1f << CLK_PMU_PCLK_DIV_SHIFT, 456 }; 457 #endif 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