1 /* 2 * (C) Copyright 2015 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #ifndef _ASM_ARCH_CRU_RK3036_H 7 #define _ASM_ARCH_CRU_RK3036_H 8 9 #include <common.h> 10 11 #define OSC_HZ (24 * 1000 * 1000) 12 13 #define APLL_HZ (600 * 1000000) 14 #define GPLL_HZ (594 * 1000000) 15 16 #define CORE_PERI_HZ 150000000 17 #define CORE_ACLK_HZ 300000000 18 19 #define BUS_ACLK_HZ 148500000 20 #define BUS_HCLK_HZ 148500000 21 #define BUS_PCLK_HZ 74250000 22 23 #define PERI_ACLK_HZ 148500000 24 #define PERI_HCLK_HZ 148500000 25 #define PERI_PCLK_HZ 74250000 26 27 /* Private data for the clock driver - used by rockchip_get_cru() */ 28 struct rk3036_clk_priv { 29 struct rk3036_cru *cru; 30 ulong rate; 31 ulong armclk_hz; 32 ulong armclk_enter_hz; 33 ulong armclk_init_hz; 34 bool sync_kernel; 35 bool set_armclk_rate; 36 }; 37 38 struct rk3036_cru { 39 struct rk3036_pll { 40 unsigned int con0; 41 unsigned int con1; 42 unsigned int con2; 43 unsigned int con3; 44 } pll[4]; 45 unsigned int cru_mode_con; 46 unsigned int cru_clksel_con[35]; 47 unsigned int cru_clkgate_con[11]; 48 unsigned int reserved; 49 unsigned int cru_glb_srst_fst_value; 50 unsigned int cru_glb_srst_snd_value; 51 unsigned int reserved1[2]; 52 unsigned int cru_softrst_con[9]; 53 unsigned int cru_misc_con; 54 unsigned int reserved2[2]; 55 unsigned int cru_glb_cnt_th; 56 unsigned int cru_sdmmc_con[2]; 57 unsigned int cru_sdio_con[2]; 58 unsigned int cru_emmc_con[2]; 59 unsigned int reserved3; 60 unsigned int cru_rst_st; 61 unsigned int reserved4[0x23]; 62 unsigned int cru_pll_mask_con; 63 }; 64 check_member(rk3036_cru, cru_pll_mask_con, 0x01f0); 65 66 struct pll_div { 67 u32 refdiv; 68 u32 fbdiv; 69 u32 postdiv1; 70 u32 postdiv2; 71 u32 frac; 72 }; 73 74 struct rk3036_clk_info { 75 unsigned long id; 76 char *name; 77 bool is_cru; 78 }; 79 80 enum { 81 /* PLLCON0*/ 82 PLL_POSTDIV1_SHIFT = 12, 83 PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT, 84 PLL_FBDIV_SHIFT = 0, 85 PLL_FBDIV_MASK = 0xfff, 86 87 /* PLLCON1 */ 88 PLL_RST_SHIFT = 14, 89 PLL_PD_SHIFT = 13, 90 PLL_PD_MASK = 1 << PLL_PD_SHIFT, 91 PLL_DSMPD_SHIFT = 12, 92 PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT, 93 PLL_LOCK_STATUS_SHIFT = 10, 94 PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT, 95 PLL_POSTDIV2_SHIFT = 6, 96 PLL_POSTDIV2_MASK = 7 << PLL_POSTDIV2_SHIFT, 97 PLL_REFDIV_SHIFT = 0, 98 PLL_REFDIV_MASK = 0x3f, 99 100 /* CRU_MODE */ 101 GPLL_MODE_SHIFT = 12, 102 GPLL_MODE_MASK = 3 << GPLL_MODE_SHIFT, 103 GPLL_MODE_SLOW = 0, 104 GPLL_MODE_NORM, 105 GPLL_MODE_DEEP, 106 DPLL_MODE_SHIFT = 4, 107 DPLL_MODE_MASK = 1 << DPLL_MODE_SHIFT, 108 DPLL_MODE_SLOW = 0, 109 DPLL_MODE_NORM, 110 APLL_MODE_SHIFT = 0, 111 APLL_MODE_MASK = 1 << APLL_MODE_SHIFT, 112 APLL_MODE_SLOW = 0, 113 APLL_MODE_NORM, 114 115 /* CRU_CLK_SEL0_CON */ 116 BUS_ACLK_PLL_SEL_SHIFT = 14, 117 BUS_ACLK_PLL_SEL_MASK = 3 << BUS_ACLK_PLL_SEL_SHIFT, 118 BUS_ACLK_PLL_SEL_APLL = 0, 119 BUS_ACLK_PLL_SEL_DPLL, 120 BUS_ACLK_PLL_SEL_GPLL, 121 BUS_ACLK_DIV_SHIFT = 8, 122 BUS_ACLK_DIV_MASK = 0x1f << BUS_ACLK_DIV_SHIFT, 123 CORE_CLK_PLL_SEL_SHIFT = 7, 124 CORE_CLK_PLL_SEL_MASK = 1 << CORE_CLK_PLL_SEL_SHIFT, 125 CORE_CLK_PLL_SEL_APLL = 0, 126 CORE_CLK_PLL_SEL_GPLL, 127 CORE_DIV_CON_SHIFT = 0, 128 CORE_DIV_CON_MASK = 0x1f << CORE_DIV_CON_SHIFT, 129 130 /* CRU_CLK_SEL1_CON */ 131 BUS_PCLK_DIV_SHIFT = 12, 132 BUS_PCLK_DIV_MASK = 7 << BUS_PCLK_DIV_SHIFT, 133 BUS_HCLK_DIV_SHIFT = 8, 134 BUS_HCLK_DIV_MASK = 3 << BUS_HCLK_DIV_SHIFT, 135 CORE_ACLK_DIV_SHIFT = 4, 136 CORE_ACLK_DIV_MASK = 7 << CORE_ACLK_DIV_SHIFT, 137 CORE_PERI_DIV_SHIFT = 0, 138 CORE_PERI_DIV_MASK = 0xf << CORE_PERI_DIV_SHIFT, 139 140 /* CRU_CLKSEL10_CON */ 141 PERI_PLL_SEL_SHIFT = 14, 142 PERI_PLL_SEL_MASK = 3 << PERI_PLL_SEL_SHIFT, 143 PERI_PLL_APLL = 0, 144 PERI_PLL_DPLL, 145 PERI_PLL_GPLL, 146 PERI_PCLK_DIV_SHIFT = 12, 147 PERI_PCLK_DIV_MASK = 3 << PERI_PCLK_DIV_SHIFT, 148 PERI_HCLK_DIV_SHIFT = 8, 149 PERI_HCLK_DIV_MASK = 3 << PERI_HCLK_DIV_SHIFT, 150 PERI_ACLK_DIV_SHIFT = 0, 151 PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT, 152 153 /* CRU_CLKSEL11_CON */ 154 SDIO_DIV_SHIFT = 8, 155 SDIO_DIV_MASK = 0x7f << SDIO_DIV_SHIFT, 156 MMC0_DIV_SHIFT = 0, 157 MMC0_DIV_MASK = 0x7f << MMC0_DIV_SHIFT, 158 159 /* CRU_CLKSEL12_CON */ 160 EMMC_PLL_SHIFT = 12, 161 EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT, 162 EMMC_SEL_APLL = 0, 163 EMMC_SEL_DPLL, 164 EMMC_SEL_GPLL, 165 EMMC_SEL_24M, 166 SDIO_PLL_SHIFT = 10, 167 SDIO_PLL_MASK = 3 << SDIO_PLL_SHIFT, 168 SDIO_SEL_APLL = 0, 169 SDIO_SEL_DPLL, 170 SDIO_SEL_GPLL, 171 SDIO_SEL_24M, 172 MMC0_PLL_SHIFT = 8, 173 MMC0_PLL_MASK = 3 << MMC0_PLL_SHIFT, 174 MMC0_SEL_APLL = 0, 175 MMC0_SEL_DPLL, 176 MMC0_SEL_GPLL, 177 MMC0_SEL_24M, 178 EMMC_DIV_SHIFT = 0, 179 EMMC_DIV_MASK = 0x7f << EMMC_DIV_SHIFT, 180 181 /* CRU_CLKSEL16_CON */ 182 NANDC_DIV_SHIFT = 10, 183 NANDC_DIV_MASK = 0x1f << NANDC_DIV_SHIFT, 184 NANDC_PLL_SHIFT = 8, 185 NANDC_PLL_MASK = 3 << NANDC_PLL_SHIFT, 186 NANDC_SEL_APLL = 0, 187 NANDC_SEL_DPLL, 188 NANDC_SEL_GPLL, 189 190 /* CLKSEL_CON25 */ 191 SPI_PLL_SEL_SHIFT = 8, 192 SPI_PLL_SEL_MASK = 0x3 << SPI_PLL_SEL_SHIFT, 193 SPI_PLL_SEL_APLL = 0, 194 SPI_PLL_SEL_DPLL, 195 SPI_PLL_SEL_GPLL, 196 SPI_DIV_SHIFT = 0, 197 SPI_DIV_MASK = 0x7f << SPI_DIV_SHIFT, 198 199 /* CRU_CLKSEL28_CON */ 200 LCDC_DCLK_DIV_SHIFT = 8, 201 LCDC_DCLK_DIV_MASK = 0xff << LCDC_DCLK_DIV_SHIFT, 202 LCDC_DCLK_SEL_SHIFT = 0, 203 LCDC_DCLK_SEL_MASK = 0x3 << LCDC_DCLK_SEL_SHIFT, 204 LCDC_DCLK_SEL_APLL = 0, 205 LCDC_DCLK_SEL_DPLL, 206 LCDC_DCLK_SEL_GPLL, 207 208 /* CRU_CLKSEL31_CON */ 209 LCDC_ACLK_SEL_SHIFT = 14, 210 LCDC_ACLK_SEL_MASK = 0x3 << LCDC_ACLK_SEL_SHIFT, 211 LCDC_ACLK_SEL_APLL = 0, 212 LCDC_ACLK_SEL_DPLL, 213 LCDC_ACLK_SEL_GPLL, 214 LCDC_ACLK_DIV_SHIFT = 8, 215 LCDC_ACLK_DIV_MASK = 0x1f << LCDC_ACLK_DIV_SHIFT, 216 217 /* CRU_SOFTRST5_CON */ 218 DDRCTRL_PSRST_SHIFT = 11, 219 DDRCTRL_SRST_SHIFT = 10, 220 DDRPHY_PSRST_SHIFT = 9, 221 DDRPHY_SRST_SHIFT = 8, 222 }; 223 #endif 224