1 /* 2 * (C) Copyright 2016 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __ASM_ARCH_CRU_RK3399_H_ 8 #define __ASM_ARCH_CRU_RK3399_H_ 9 10 #include <common.h> 11 12 /* Private data for the clock driver - used by rockchip_get_cru() */ 13 struct rk3399_clk_priv { 14 struct rk3399_cru *cru; 15 ulong armlclk_hz; 16 ulong armlclk_enter_hz; 17 ulong armlclk_init_hz; 18 ulong armbclk_hz; 19 ulong armbclk_enter_hz; 20 ulong armbclk_init_hz; 21 bool sync_kernel; 22 bool set_armclk_rate; 23 }; 24 25 struct rk3399_pmuclk_priv { 26 struct rk3399_pmucru *pmucru; 27 }; 28 29 struct rk3399_pmucru { 30 u32 ppll_con[6]; 31 u32 reserved[0x1a]; 32 u32 pmucru_clksel[6]; 33 u32 pmucru_clkfrac_con[2]; 34 u32 reserved2[0x18]; 35 u32 pmucru_clkgate_con[3]; 36 u32 reserved3; 37 u32 pmucru_softrst_con[2]; 38 u32 reserved4[2]; 39 u32 pmucru_rstnhold_con[2]; 40 u32 reserved5[2]; 41 u32 pmucru_gatedis_con[2]; 42 }; 43 check_member(rk3399_pmucru, pmucru_gatedis_con[1], 0x134); 44 45 struct rk3399_cru { 46 u32 apll_l_con[6]; 47 u32 reserved[2]; 48 u32 apll_b_con[6]; 49 u32 reserved1[2]; 50 u32 dpll_con[6]; 51 u32 reserved2[2]; 52 u32 cpll_con[6]; 53 u32 reserved3[2]; 54 u32 gpll_con[6]; 55 u32 reserved4[2]; 56 u32 npll_con[6]; 57 u32 reserved5[2]; 58 u32 vpll_con[6]; 59 u32 reserved6[0x0a]; 60 u32 clksel_con[108]; 61 u32 reserved7[0x14]; 62 u32 clkgate_con[35]; 63 u32 reserved8[0x1d]; 64 u32 softrst_con[21]; 65 u32 reserved9[0x2b]; 66 u32 glb_srst_fst_value; 67 u32 glb_srst_snd_value; 68 u32 glb_cnt_th; 69 u32 misc_con; 70 u32 glb_rst_con; 71 u32 glb_rst_st; 72 u32 reserved10[0x1a]; 73 u32 sdmmc_con[2]; 74 u32 sdio0_con[2]; 75 u32 sdio1_con[2]; 76 }; 77 check_member(rk3399_cru, sdio1_con[1], 0x594); 78 #define MHz 1000000 79 #define KHz 1000 80 #define OSC_HZ (24*MHz) 81 #define APLL_HZ (600*MHz) 82 #define GPLL_HZ (800 * MHz) 83 #define CPLL_HZ (384*MHz) 84 #define NPLL_HZ (600 * MHz) 85 #define PPLL_HZ (676*MHz) 86 87 #define PMU_PCLK_HZ (48*MHz) 88 89 #define ACLKM_CORE_HZ (300*MHz) 90 #define ATCLK_CORE_HZ (300*MHz) 91 #define PCLK_DBG_HZ (100*MHz) 92 93 #define PERIHP_ACLK_HZ (150 * MHz) 94 #define PERIHP_HCLK_HZ (75 * MHz) 95 #define PERIHP_PCLK_HZ (37500 * KHz) 96 97 #define PERILP0_ACLK_HZ (300 * MHz) 98 #define PERILP0_HCLK_HZ (100 * MHz) 99 #define PERILP0_PCLK_HZ (50 * MHz) 100 101 #define PERILP1_HCLK_HZ (100 * MHz) 102 #define PERILP1_PCLK_HZ (50 * MHz) 103 104 #define PWM_CLOCK_HZ PMU_PCLK_HZ 105 106 enum apll_frequencies { 107 APLL_1600_MHZ, 108 APLL_816_MHZ, 109 APLL_600_MHZ, 110 }; 111 112 enum cpu_cluster { 113 CPU_CLUSTER_LITTLE, 114 CPU_CLUSTER_BIG, 115 }; 116 117 enum rk3399_pll_id { 118 APLLL_ID = 0, 119 APLLB_ID, 120 DPLL_ID, 121 CPLL_ID, 122 GPLL_ID, 123 NPLL_ID, 124 VPLL_ID, 125 126 PPLL_ID, 127 128 END_PLL_ID 129 }; 130 131 struct rk3399_clk_info { 132 unsigned long id; 133 char *name; 134 bool is_cru; 135 }; 136 137 #endif /* __ASM_ARCH_CRU_RK3399_H_ */ 138