1 /* 2 * (C) Copyright 2016 Heiko Stuebner <heiko@sntech.de> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #ifndef _ASM_ARCH_CRU_RK3066_H 7 #define _ASM_ARCH_CRU_RK3066_H 8 9 #define OSC_HZ (24 * 1000 * 1000) 10 11 #define APLL_HZ (1416 * 1000000) 12 #define APLL_SAFE_HZ (600 * 1000000) 13 #define GPLL_HZ (594 * 1000000) 14 #define CPLL_HZ (384 * 1000000) 15 16 /* The SRAM is clocked off aclk_cpu, so we want to max it out for boot speed */ 17 #define CPU_ACLK_HZ 297000000 18 #define CPU_HCLK_HZ 148500000 19 #define CPU_PCLK_HZ 74250000 20 #define CPU_H2P_HZ 74250000 21 22 #define PERI_ACLK_HZ 148500000 23 #define PERI_HCLK_HZ 148500000 24 #define PERI_PCLK_HZ 74250000 25 26 /* Private data for the clock driver - used by rockchip_get_cru() */ 27 struct rk3066_clk_priv { 28 struct rk3066_grf *grf; 29 struct rk3066_cru *cru; 30 ulong rate; 31 bool has_bwadj; 32 ulong armclk_hz; 33 ulong armclk_enter_hz; 34 ulong armclk_init_hz; 35 bool sync_kernel; 36 bool set_armclk_rate; 37 }; 38 39 struct rk3066_cru { 40 struct rk3066_pll { 41 u32 con0; 42 u32 con1; 43 u32 con2; 44 u32 con3; 45 } pll[4]; 46 u32 cru_mode_con; 47 u32 cru_clksel_con[35]; 48 u32 cru_clkgate_con[10]; 49 u32 reserved1[2]; 50 u32 cru_glb_srst_fst_value; 51 u32 cru_glb_srst_snd_value; 52 u32 reserved2[2]; 53 u32 cru_softrst_con[9]; 54 u32 cru_misc_con; 55 u32 reserved3[2]; 56 u32 cru_glb_cnt_th; 57 }; 58 check_member(rk3066_cru, cru_glb_cnt_th, 0x0140); 59 60 struct rk3066_clk_info { 61 unsigned long id; 62 char *name; 63 bool is_cru; 64 }; 65 66 /* CRU_CLKSEL0_CON */ 67 enum { 68 /* a9_core_div: core = core_src / (a9_core_div + 1) */ 69 A9_CORE_DIV_SHIFT = 9, 70 A9_CORE_DIV_MASK = 0x1f << A9_CORE_DIV_SHIFT, 71 CORE_PLL_SHIFT = 8, 72 CORE_PLL_MASK = 1 << CORE_PLL_SHIFT, 73 CORE_PLL_SELECT_APLL = 0, 74 CORE_PLL_SELECT_GPLL, 75 76 /* core peri div: core:core_peri = 2:1, 4:1, 8:1 or 16:1 */ 77 CORE_PERI_DIV_SHIFT = 6, 78 CORE_PERI_DIV_MASK = 3 << CORE_PERI_DIV_SHIFT, 79 80 /* aclk_cpu pll selection */ 81 CPU_ACLK_PLL_SHIFT = 5, 82 CPU_ACLK_PLL_MASK = 1 << CPU_ACLK_PLL_SHIFT, 83 CPU_ACLK_PLL_SELECT_APLL = 0, 84 CPU_ACLK_PLL_SELECT_GPLL, 85 86 /* a9_cpu_div: aclk_cpu = cpu_src / (a9_cpu_div + 1) */ 87 A9_CPU_DIV_SHIFT = 0, 88 A9_CPU_DIV_MASK = 0x1f << A9_CPU_DIV_SHIFT, 89 }; 90 91 /* CRU_CLKSEL1_CON */ 92 enum { 93 /* ahb2apb_pclk_div: hclk_cpu:pclk_cpu = 1:1, 2:1 or 4:1 */ 94 AHB2APB_DIV_SHIFT = 14, 95 AHB2APB_DIV_MASK = 3 << AHB2APB_DIV_SHIFT, 96 97 /* cpu_pclk_div: aclk_cpu:pclk_cpu = 1:1, 2:1, 4:1 or 8:1 */ 98 CPU_PCLK_DIV_SHIFT = 12, 99 CPU_PCLK_DIV_MASK = 3 << CPU_PCLK_DIV_SHIFT, 100 101 /* cpu_hclk_div: aclk_cpu:hclk_cpu = 1:1, 2:1 or 4:1 */ 102 CPU_HCLK_DIV_SHIFT = 8, 103 CPU_HCLK_DIV_MASK = 3 << CPU_HCLK_DIV_SHIFT, 104 105 /* core_aclk_div: cire:aclk_core = 1:1, 2:1, 3:1, 4:1 or 8:1 */ 106 CORE_ACLK_DIV_SHIFT = 3, 107 CORE_ACLK_DIV_MASK = 7 << CORE_ACLK_DIV_SHIFT, 108 }; 109 110 /* CRU_CLKSEL10_CON */ 111 enum { 112 PERI_SEL_PLL_SHIFT = 15, 113 PERI_SEL_PLL_MASK = 1 << PERI_SEL_PLL_SHIFT, 114 PERI_SEL_CPLL = 0, 115 PERI_SEL_GPLL, 116 117 /* peri pclk div: aclk_bus:pclk_bus = 1:1, 2:1, 4:1 or 8:1 */ 118 PERI_PCLK_DIV_SHIFT = 12, 119 PERI_PCLK_DIV_MASK = 3 << PERI_PCLK_DIV_SHIFT, 120 121 /* peripheral bus hclk div:aclk_bus: hclk_bus = 1:1, 2:1 or 4:1 */ 122 PERI_HCLK_DIV_SHIFT = 8, 123 PERI_HCLK_DIV_MASK = 3 << PERI_HCLK_DIV_SHIFT, 124 125 /* peri aclk div: aclk_peri = periph_src / (peri_aclk_div + 1) */ 126 PERI_ACLK_DIV_SHIFT = 0, 127 PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT, 128 }; 129 /* CRU_CLKSEL11_CON */ 130 enum { 131 MMC0_DIV_SHIFT = 0, 132 MMC0_DIV_MASK = 0x3f << MMC0_DIV_SHIFT, 133 }; 134 135 /* CRU_CLKSEL12_CON */ 136 enum { 137 UART_PLL_SHIFT = 15, 138 UART_PLL_MASK = 1 << UART_PLL_SHIFT, 139 UART_PLL_SELECT_GENERAL = 0, 140 UART_PLL_SELECT_CODEC, 141 142 EMMC_DIV_SHIFT = 8, 143 EMMC_DIV_MASK = 0x3f << EMMC_DIV_SHIFT, 144 145 SDIO_DIV_SHIFT = 0, 146 SDIO_DIV_MASK = 0x3f << SDIO_DIV_SHIFT, 147 }; 148 149 /* CRU_CLKSEL25_CON */ 150 enum { 151 SPI1_DIV_SHIFT = 8, 152 SPI1_DIV_MASK = 0x7f << SPI1_DIV_SHIFT, 153 154 SPI0_DIV_SHIFT = 0, 155 SPI0_DIV_MASK = 0x7f << SPI0_DIV_SHIFT, 156 }; 157 158 /* CRU_MODE_CON */ 159 enum { 160 GPLL_MODE_SHIFT = 12, 161 GPLL_MODE_MASK = 3 << GPLL_MODE_SHIFT, 162 GPLL_MODE_SLOW = 0, 163 GPLL_MODE_NORMAL, 164 GPLL_MODE_DEEP, 165 166 CPLL_MODE_SHIFT = 8, 167 CPLL_MODE_MASK = 3 << CPLL_MODE_SHIFT, 168 CPLL_MODE_SLOW = 0, 169 CPLL_MODE_NORMAL, 170 CPLL_MODE_DEEP, 171 172 DPLL_MODE_SHIFT = 4, 173 DPLL_MODE_MASK = 3 << DPLL_MODE_SHIFT, 174 DPLL_MODE_SLOW = 0, 175 DPLL_MODE_NORMAL, 176 DPLL_MODE_DEEP, 177 178 APLL_MODE_SHIFT = 0, 179 APLL_MODE_MASK = 3 << APLL_MODE_SHIFT, 180 APLL_MODE_SLOW = 0, 181 APLL_MODE_NORMAL, 182 APLL_MODE_DEEP, 183 }; 184 185 /* CRU_APLL_CON0 */ 186 enum { 187 CLKR_SHIFT = 8, 188 CLKR_MASK = 0x3f << CLKR_SHIFT, 189 190 CLKOD_SHIFT = 0, 191 CLKOD_MASK = 0x3f << CLKOD_SHIFT, 192 }; 193 194 /* CRU_APLL_CON1 */ 195 enum { 196 CLKF_SHIFT = 0, 197 CLKF_MASK = 0x1fff << CLKF_SHIFT, 198 }; 199 200 #endif 201