1 /* 2 * (C) Copyright 2015 Google, Inc 3 * 4 * (C) Copyright 2008-2014 Rockchip Electronics 5 * Peter, Software Engineering, <superpeter.cai@gmail.com>. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 #ifndef _ASM_ARCH_CRU_RK3288_H 10 #define _ASM_ARCH_CRU_RK3288_H 11 12 #define OSC_HZ (24 * 1000 * 1000) 13 14 #define APLL_HZ (1800 * 1000000) 15 #define GPLL_HZ (594 * 1000000) 16 #define CPLL_HZ (384 * 1000000) 17 #define NPLL_HZ (384 * 1000000) 18 19 /* The SRAM is clocked off aclk_bus, so we want to max it out for boot speed */ 20 #define PD_BUS_ACLK_HZ 297000000 21 #define PD_BUS_HCLK_HZ 148500000 22 #define PD_BUS_PCLK_HZ 74250000 23 24 #define PERI_ACLK_HZ 148500000 25 #define PERI_HCLK_HZ 148500000 26 #define PERI_PCLK_HZ 74250000 27 28 #define HCLK_VIO_HZ 100000000 29 30 /* Private data for the clock driver - used by rockchip_get_cru() */ 31 struct rk3288_clk_priv { 32 struct rk3288_grf *grf; 33 struct rk3288_cru *cru; 34 ulong rate; 35 ulong armclk_hz; 36 ulong armclk_enter_hz; 37 ulong armclk_init_hz; 38 bool sync_kernel; 39 bool set_armclk_rate; 40 }; 41 42 struct rk3288_cru { 43 struct rk3288_pll { 44 u32 con0; 45 u32 con1; 46 u32 con2; 47 u32 con3; 48 } pll[5]; 49 u32 cru_mode_con; 50 u32 reserved0[3]; 51 u32 cru_clksel_con[43]; 52 u32 reserved1[21]; 53 u32 cru_clkgate_con[19]; 54 u32 reserved2; 55 u32 cru_glb_srst_fst_value; 56 u32 cru_glb_srst_snd_value; 57 u32 cru_softrst_con[12]; 58 u32 cru_misc_con; 59 u32 cru_glb_cnt_th; 60 u32 cru_glb_rst_con; 61 u32 reserved3; 62 u32 cru_glb_rst_st; 63 u32 reserved4; 64 u32 cru_sdmmc_con[2]; 65 u32 cru_sdio0_con[2]; 66 u32 cru_sdio1_con[2]; 67 u32 cru_emmc_con[2]; 68 }; 69 check_member(rk3288_cru, cru_emmc_con[1], 0x021c); 70 71 struct rk3288_clk_info { 72 unsigned long id; 73 char *name; 74 bool is_cru; 75 }; 76 77 /* CRU_CLKSEL11_CON */ 78 enum { 79 HSICPHY_DIV_SHIFT = 8, 80 HSICPHY_DIV_MASK = 0x3f << HSICPHY_DIV_SHIFT, 81 82 MMC0_PLL_SHIFT = 6, 83 MMC0_PLL_MASK = 3 << MMC0_PLL_SHIFT, 84 MMC0_PLL_SELECT_CODEC = 0, 85 MMC0_PLL_SELECT_GENERAL, 86 MMC0_PLL_SELECT_24MHZ, 87 88 MMC0_DIV_SHIFT = 0, 89 MMC0_DIV_MASK = 0x3f << MMC0_DIV_SHIFT, 90 }; 91 92 /* CRU_CLKSEL12_CON */ 93 enum { 94 EMMC_PLL_SHIFT = 0xe, 95 EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT, 96 EMMC_PLL_SELECT_CODEC = 0, 97 EMMC_PLL_SELECT_GENERAL, 98 EMMC_PLL_SELECT_24MHZ, 99 100 EMMC_DIV_SHIFT = 8, 101 EMMC_DIV_MASK = 0x3f << EMMC_DIV_SHIFT, 102 103 SDIO0_PLL_SHIFT = 6, 104 SDIO0_PLL_MASK = 3 << SDIO0_PLL_SHIFT, 105 SDIO0_PLL_SELECT_CODEC = 0, 106 SDIO0_PLL_SELECT_GENERAL, 107 SDIO0_PLL_SELECT_24MHZ, 108 109 SDIO0_DIV_SHIFT = 0, 110 SDIO0_DIV_MASK = 0x3f << SDIO0_DIV_SHIFT, 111 }; 112 113 /* CRU_CLKSEL21_CON */ 114 enum { 115 MAC_DIV_CON_SHIFT = 0xf, 116 MAC_DIV_CON_MASK = 0x1f << MAC_DIV_CON_SHIFT, 117 118 RMII_EXTCLK_SHIFT = 4, 119 RMII_EXTCLK_MASK = 1 << RMII_EXTCLK_SHIFT, 120 RMII_EXTCLK_SELECT_INT_DIV_CLK = 0, 121 RMII_EXTCLK_SELECT_EXT_CLK = 1, 122 123 EMAC_PLL_SHIFT = 0, 124 EMAC_PLL_MASK = 0x3 << EMAC_PLL_SHIFT, 125 EMAC_PLL_SELECT_NEW = 0x0, 126 EMAC_PLL_SELECT_CODEC = 0x1, 127 EMAC_PLL_SELECT_GENERAL = 0x2, 128 }; 129 130 /* CRU_CLKSEL25_CON */ 131 enum { 132 SPI1_PLL_SHIFT = 0xf, 133 SPI1_PLL_MASK = 1 << SPI1_PLL_SHIFT, 134 SPI1_PLL_SELECT_CODEC = 0, 135 SPI1_PLL_SELECT_GENERAL, 136 137 SPI1_DIV_SHIFT = 8, 138 SPI1_DIV_MASK = 0x7f << SPI1_DIV_SHIFT, 139 140 SPI0_PLL_SHIFT = 7, 141 SPI0_PLL_MASK = 1 << SPI0_PLL_SHIFT, 142 SPI0_PLL_SELECT_CODEC = 0, 143 SPI0_PLL_SELECT_GENERAL, 144 145 SPI0_DIV_SHIFT = 0, 146 SPI0_DIV_MASK = 0x7f << SPI0_DIV_SHIFT, 147 }; 148 149 /* CRU_CLKSEL27_CON */ 150 enum { 151 DCLK_VOP0_DIV_SHIFT = 8, 152 DCLK_VOP0_DIV_MASK = 0xff << DCLK_VOP0_DIV_SHIFT, 153 DCLK_VOP0_PLL_SHIFT = 0, 154 DCLK_VOP0_PLL_MASK = 3 << DCLK_VOP0_PLL_SHIFT, 155 DCLK_VOP0_SELECT_CPLL = 0, 156 DCLK_VOP0_SELECT_GPLL = 1, 157 DCLK_VOP0_SELECT_NPLL = 2, 158 }; 159 160 /* CRU_CLKSEL28_CON */ 161 enum { 162 HCLK_VIO_DIV_SHIFT = 8, 163 HCLK_VIO_DIV_MASK = 0x1f << HCLK_VIO_DIV_SHIFT, 164 }; 165 166 /* CRU_CLKSEL29_CON */ 167 enum { 168 DCLK_VOP1_DIV_SHIFT = 8, 169 DCLK_VOP1_DIV_MASK = 0xff << DCLK_VOP1_DIV_SHIFT, 170 DCLK_VOP1_PLL_SHIFT = 6, 171 DCLK_VOP1_PLL_MASK = 3 << DCLK_VOP1_PLL_SHIFT, 172 DCLK_VOP1_SELECT_CPLL = 0, 173 DCLK_VOP1_SELECT_GPLL = 1, 174 DCLK_VOP1_SELECT_NPLL = 2, 175 }; 176 177 /* CRU_CLKSEL31_CON */ 178 enum { 179 ACLK_VIO_SELECT_CPLL = 0, 180 ACLK_VIO_SELECT_GPLL = 1, 181 ACLK_VIO_SELECT_USB480 = 2, 182 ACLK_VIO1_PLL_SHIFT = 14, 183 ACLK_VIO1_PLL_MASK = 3 << ACLK_VIO1_PLL_SHIFT, 184 ACLK_VIO1_DIV_SHIFT = 8, 185 ACLK_VIO1_DIV_MASK = 0x1f << ACLK_VIO1_DIV_SHIFT, 186 ACLK_VIO0_PLL_SHIFT = 6, 187 ACLK_VIO0_PLL_MASK = 3 << ACLK_VIO0_PLL_SHIFT, 188 ACLK_VIO0_DIV_SHIFT = 0, 189 ACLK_VIO0_DIV_MASK = 0x1f << ACLK_VIO0_DIV_SHIFT, 190 }; 191 192 /* CRU_CLKSEL37_CON */ 193 enum { 194 PCLK_CORE_DBG_DIV_SHIFT = 9, 195 PCLK_CORE_DBG_DIV_MASK = 0x1f << PCLK_CORE_DBG_DIV_SHIFT, 196 197 ATCLK_CORE_DIV_CON_SHIFT = 4, 198 ATCLK_CORE_DIV_CON_MASK = 0x1f << ATCLK_CORE_DIV_CON_SHIFT, 199 200 CLK_L2RAM_DIV_SHIFT = 0, 201 CLK_L2RAM_DIV_MASK = 7 << CLK_L2RAM_DIV_SHIFT, 202 }; 203 204 /* CRU_CLKSEL39_CON */ 205 enum { 206 ACLK_HEVC_PLL_SHIFT = 0xe, 207 ACLK_HEVC_PLL_MASK = 3 << ACLK_HEVC_PLL_SHIFT, 208 ACLK_HEVC_PLL_SELECT_CODEC = 0, 209 ACLK_HEVC_PLL_SELECT_GENERAL, 210 ACLK_HEVC_PLL_SELECT_NEW, 211 212 ACLK_HEVC_DIV_SHIFT = 8, 213 ACLK_HEVC_DIV_MASK = 0x1f << ACLK_HEVC_DIV_SHIFT, 214 215 SPI2_PLL_SHIFT = 7, 216 SPI2_PLL_MASK = 1 << SPI2_PLL_SHIFT, 217 SPI2_PLL_SELECT_CODEC = 0, 218 SPI2_PLL_SELECT_GENERAL, 219 220 SPI2_DIV_SHIFT = 0, 221 SPI2_DIV_MASK = 0x7f << SPI2_DIV_SHIFT, 222 }; 223 224 /* CRU_MODE_CON */ 225 enum { 226 CRU_MODE_MASK = 3, 227 228 NPLL_MODE_SHIFT = 0xe, 229 NPLL_MODE_MASK = CRU_MODE_MASK << NPLL_MODE_SHIFT, 230 NPLL_MODE_SLOW = 0, 231 NPLL_MODE_NORMAL, 232 NPLL_MODE_DEEP, 233 234 GPLL_MODE_SHIFT = 0xc, 235 GPLL_MODE_MASK = CRU_MODE_MASK << GPLL_MODE_SHIFT, 236 GPLL_MODE_SLOW = 0, 237 GPLL_MODE_NORMAL, 238 GPLL_MODE_DEEP, 239 240 CPLL_MODE_SHIFT = 8, 241 CPLL_MODE_MASK = CRU_MODE_MASK << CPLL_MODE_SHIFT, 242 CPLL_MODE_SLOW = 0, 243 CPLL_MODE_NORMAL, 244 CPLL_MODE_DEEP, 245 246 DPLL_MODE_SHIFT = 4, 247 DPLL_MODE_MASK = CRU_MODE_MASK << DPLL_MODE_SHIFT, 248 DPLL_MODE_SLOW = 0, 249 DPLL_MODE_NORMAL, 250 DPLL_MODE_DEEP, 251 252 APLL_MODE_SHIFT = 0, 253 APLL_MODE_MASK = CRU_MODE_MASK << APLL_MODE_SHIFT, 254 APLL_MODE_SLOW = 0, 255 APLL_MODE_NORMAL, 256 APLL_MODE_DEEP, 257 }; 258 259 /* CRU_APLL_CON0 */ 260 enum { 261 CLKR_SHIFT = 8, 262 CLKR_MASK = 0x3f << CLKR_SHIFT, 263 264 CLKOD_SHIFT = 0, 265 CLKOD_MASK = 0xf << CLKOD_SHIFT, 266 }; 267 268 /* CRU_APLL_CON1 */ 269 enum { 270 LOCK_SHIFT = 0x1f, 271 LOCK_MASK = 1 << LOCK_SHIFT, 272 LOCK_UNLOCK = 0, 273 LOCK_LOCK, 274 275 CLKF_SHIFT = 0, 276 CLKF_MASK = 0x1fff << CLKF_SHIFT, 277 }; 278 279 /* CRU_GLB_RST_ST */ 280 enum { 281 GLB_POR_RST, 282 FST_GLB_RST_ST = BIT(0), 283 SND_GLB_RST_ST = BIT(1), 284 FST_GLB_TSADC_RST_ST = BIT(2), 285 SND_GLB_TSADC_RST_ST = BIT(3), 286 FST_GLB_WDT_RST_ST = BIT(4), 287 SND_GLB_WDT_RST_ST = BIT(5), 288 GLB_RST_ST_MASK = GENMASK(5, 0), 289 }; 290 291 #endif 292