1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2015 Rockchip Electronics Co., Ltd 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun #ifndef _ASM_ARCH_CRU_RK3036_H 7*4882a593Smuzhiyun #define _ASM_ARCH_CRU_RK3036_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <common.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define OSC_HZ (24 * 1000 * 1000) 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define APLL_HZ (600 * 1000000) 14*4882a593Smuzhiyun #define GPLL_HZ (594 * 1000000) 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define CORE_PERI_HZ 150000000 17*4882a593Smuzhiyun #define CORE_ACLK_HZ 300000000 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define BUS_ACLK_HZ 148500000 20*4882a593Smuzhiyun #define BUS_HCLK_HZ 148500000 21*4882a593Smuzhiyun #define BUS_PCLK_HZ 74250000 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define PERI_ACLK_HZ 148500000 24*4882a593Smuzhiyun #define PERI_HCLK_HZ 148500000 25*4882a593Smuzhiyun #define PERI_PCLK_HZ 74250000 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* Private data for the clock driver - used by rockchip_get_cru() */ 28*4882a593Smuzhiyun struct rk3036_clk_priv { 29*4882a593Smuzhiyun struct rk3036_cru *cru; 30*4882a593Smuzhiyun ulong rate; 31*4882a593Smuzhiyun ulong armclk_hz; 32*4882a593Smuzhiyun ulong armclk_enter_hz; 33*4882a593Smuzhiyun ulong armclk_init_hz; 34*4882a593Smuzhiyun bool sync_kernel; 35*4882a593Smuzhiyun bool set_armclk_rate; 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun struct rk3036_cru { 39*4882a593Smuzhiyun struct rk3036_pll { 40*4882a593Smuzhiyun unsigned int con0; 41*4882a593Smuzhiyun unsigned int con1; 42*4882a593Smuzhiyun unsigned int con2; 43*4882a593Smuzhiyun unsigned int con3; 44*4882a593Smuzhiyun } pll[4]; 45*4882a593Smuzhiyun unsigned int cru_mode_con; 46*4882a593Smuzhiyun unsigned int cru_clksel_con[35]; 47*4882a593Smuzhiyun unsigned int cru_clkgate_con[11]; 48*4882a593Smuzhiyun unsigned int reserved; 49*4882a593Smuzhiyun unsigned int cru_glb_srst_fst_value; 50*4882a593Smuzhiyun unsigned int cru_glb_srst_snd_value; 51*4882a593Smuzhiyun unsigned int reserved1[2]; 52*4882a593Smuzhiyun unsigned int cru_softrst_con[9]; 53*4882a593Smuzhiyun unsigned int cru_misc_con; 54*4882a593Smuzhiyun unsigned int reserved2[2]; 55*4882a593Smuzhiyun unsigned int cru_glb_cnt_th; 56*4882a593Smuzhiyun unsigned int cru_sdmmc_con[2]; 57*4882a593Smuzhiyun unsigned int cru_sdio_con[2]; 58*4882a593Smuzhiyun unsigned int cru_emmc_con[2]; 59*4882a593Smuzhiyun unsigned int reserved3; 60*4882a593Smuzhiyun unsigned int cru_rst_st; 61*4882a593Smuzhiyun unsigned int reserved4[0x23]; 62*4882a593Smuzhiyun unsigned int cru_pll_mask_con; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun check_member(rk3036_cru, cru_pll_mask_con, 0x01f0); 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun struct pll_div { 67*4882a593Smuzhiyun u32 refdiv; 68*4882a593Smuzhiyun u32 fbdiv; 69*4882a593Smuzhiyun u32 postdiv1; 70*4882a593Smuzhiyun u32 postdiv2; 71*4882a593Smuzhiyun u32 frac; 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun struct rk3036_clk_info { 75*4882a593Smuzhiyun unsigned long id; 76*4882a593Smuzhiyun char *name; 77*4882a593Smuzhiyun bool is_cru; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun enum { 81*4882a593Smuzhiyun /* PLLCON0*/ 82*4882a593Smuzhiyun PLL_POSTDIV1_SHIFT = 12, 83*4882a593Smuzhiyun PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT, 84*4882a593Smuzhiyun PLL_FBDIV_SHIFT = 0, 85*4882a593Smuzhiyun PLL_FBDIV_MASK = 0xfff, 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun /* PLLCON1 */ 88*4882a593Smuzhiyun PLL_RST_SHIFT = 14, 89*4882a593Smuzhiyun PLL_PD_SHIFT = 13, 90*4882a593Smuzhiyun PLL_PD_MASK = 1 << PLL_PD_SHIFT, 91*4882a593Smuzhiyun PLL_DSMPD_SHIFT = 12, 92*4882a593Smuzhiyun PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT, 93*4882a593Smuzhiyun PLL_LOCK_STATUS_SHIFT = 10, 94*4882a593Smuzhiyun PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT, 95*4882a593Smuzhiyun PLL_POSTDIV2_SHIFT = 6, 96*4882a593Smuzhiyun PLL_POSTDIV2_MASK = 7 << PLL_POSTDIV2_SHIFT, 97*4882a593Smuzhiyun PLL_REFDIV_SHIFT = 0, 98*4882a593Smuzhiyun PLL_REFDIV_MASK = 0x3f, 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun /* CRU_MODE */ 101*4882a593Smuzhiyun GPLL_MODE_SHIFT = 12, 102*4882a593Smuzhiyun GPLL_MODE_MASK = 3 << GPLL_MODE_SHIFT, 103*4882a593Smuzhiyun GPLL_MODE_SLOW = 0, 104*4882a593Smuzhiyun GPLL_MODE_NORM, 105*4882a593Smuzhiyun GPLL_MODE_DEEP, 106*4882a593Smuzhiyun DPLL_MODE_SHIFT = 4, 107*4882a593Smuzhiyun DPLL_MODE_MASK = 1 << DPLL_MODE_SHIFT, 108*4882a593Smuzhiyun DPLL_MODE_SLOW = 0, 109*4882a593Smuzhiyun DPLL_MODE_NORM, 110*4882a593Smuzhiyun APLL_MODE_SHIFT = 0, 111*4882a593Smuzhiyun APLL_MODE_MASK = 1 << APLL_MODE_SHIFT, 112*4882a593Smuzhiyun APLL_MODE_SLOW = 0, 113*4882a593Smuzhiyun APLL_MODE_NORM, 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun /* CRU_CLK_SEL0_CON */ 116*4882a593Smuzhiyun BUS_ACLK_PLL_SEL_SHIFT = 14, 117*4882a593Smuzhiyun BUS_ACLK_PLL_SEL_MASK = 3 << BUS_ACLK_PLL_SEL_SHIFT, 118*4882a593Smuzhiyun BUS_ACLK_PLL_SEL_APLL = 0, 119*4882a593Smuzhiyun BUS_ACLK_PLL_SEL_DPLL, 120*4882a593Smuzhiyun BUS_ACLK_PLL_SEL_GPLL, 121*4882a593Smuzhiyun BUS_ACLK_DIV_SHIFT = 8, 122*4882a593Smuzhiyun BUS_ACLK_DIV_MASK = 0x1f << BUS_ACLK_DIV_SHIFT, 123*4882a593Smuzhiyun CORE_CLK_PLL_SEL_SHIFT = 7, 124*4882a593Smuzhiyun CORE_CLK_PLL_SEL_MASK = 1 << CORE_CLK_PLL_SEL_SHIFT, 125*4882a593Smuzhiyun CORE_CLK_PLL_SEL_APLL = 0, 126*4882a593Smuzhiyun CORE_CLK_PLL_SEL_GPLL, 127*4882a593Smuzhiyun CORE_DIV_CON_SHIFT = 0, 128*4882a593Smuzhiyun CORE_DIV_CON_MASK = 0x1f << CORE_DIV_CON_SHIFT, 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun /* CRU_CLK_SEL1_CON */ 131*4882a593Smuzhiyun BUS_PCLK_DIV_SHIFT = 12, 132*4882a593Smuzhiyun BUS_PCLK_DIV_MASK = 7 << BUS_PCLK_DIV_SHIFT, 133*4882a593Smuzhiyun BUS_HCLK_DIV_SHIFT = 8, 134*4882a593Smuzhiyun BUS_HCLK_DIV_MASK = 3 << BUS_HCLK_DIV_SHIFT, 135*4882a593Smuzhiyun CORE_ACLK_DIV_SHIFT = 4, 136*4882a593Smuzhiyun CORE_ACLK_DIV_MASK = 7 << CORE_ACLK_DIV_SHIFT, 137*4882a593Smuzhiyun CORE_PERI_DIV_SHIFT = 0, 138*4882a593Smuzhiyun CORE_PERI_DIV_MASK = 0xf << CORE_PERI_DIV_SHIFT, 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun /* CRU_CLKSEL10_CON */ 141*4882a593Smuzhiyun PERI_PLL_SEL_SHIFT = 14, 142*4882a593Smuzhiyun PERI_PLL_SEL_MASK = 3 << PERI_PLL_SEL_SHIFT, 143*4882a593Smuzhiyun PERI_PLL_APLL = 0, 144*4882a593Smuzhiyun PERI_PLL_DPLL, 145*4882a593Smuzhiyun PERI_PLL_GPLL, 146*4882a593Smuzhiyun PERI_PCLK_DIV_SHIFT = 12, 147*4882a593Smuzhiyun PERI_PCLK_DIV_MASK = 3 << PERI_PCLK_DIV_SHIFT, 148*4882a593Smuzhiyun PERI_HCLK_DIV_SHIFT = 8, 149*4882a593Smuzhiyun PERI_HCLK_DIV_MASK = 3 << PERI_HCLK_DIV_SHIFT, 150*4882a593Smuzhiyun PERI_ACLK_DIV_SHIFT = 0, 151*4882a593Smuzhiyun PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT, 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun /* CRU_CLKSEL11_CON */ 154*4882a593Smuzhiyun SDIO_DIV_SHIFT = 8, 155*4882a593Smuzhiyun SDIO_DIV_MASK = 0x7f << SDIO_DIV_SHIFT, 156*4882a593Smuzhiyun MMC0_DIV_SHIFT = 0, 157*4882a593Smuzhiyun MMC0_DIV_MASK = 0x7f << MMC0_DIV_SHIFT, 158*4882a593Smuzhiyun 159*4882a593Smuzhiyun /* CRU_CLKSEL12_CON */ 160*4882a593Smuzhiyun EMMC_PLL_SHIFT = 12, 161*4882a593Smuzhiyun EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT, 162*4882a593Smuzhiyun EMMC_SEL_APLL = 0, 163*4882a593Smuzhiyun EMMC_SEL_DPLL, 164*4882a593Smuzhiyun EMMC_SEL_GPLL, 165*4882a593Smuzhiyun EMMC_SEL_24M, 166*4882a593Smuzhiyun SDIO_PLL_SHIFT = 10, 167*4882a593Smuzhiyun SDIO_PLL_MASK = 3 << SDIO_PLL_SHIFT, 168*4882a593Smuzhiyun SDIO_SEL_APLL = 0, 169*4882a593Smuzhiyun SDIO_SEL_DPLL, 170*4882a593Smuzhiyun SDIO_SEL_GPLL, 171*4882a593Smuzhiyun SDIO_SEL_24M, 172*4882a593Smuzhiyun MMC0_PLL_SHIFT = 8, 173*4882a593Smuzhiyun MMC0_PLL_MASK = 3 << MMC0_PLL_SHIFT, 174*4882a593Smuzhiyun MMC0_SEL_APLL = 0, 175*4882a593Smuzhiyun MMC0_SEL_DPLL, 176*4882a593Smuzhiyun MMC0_SEL_GPLL, 177*4882a593Smuzhiyun MMC0_SEL_24M, 178*4882a593Smuzhiyun EMMC_DIV_SHIFT = 0, 179*4882a593Smuzhiyun EMMC_DIV_MASK = 0x7f << EMMC_DIV_SHIFT, 180*4882a593Smuzhiyun 181*4882a593Smuzhiyun /* CRU_CLKSEL16_CON */ 182*4882a593Smuzhiyun NANDC_DIV_SHIFT = 10, 183*4882a593Smuzhiyun NANDC_DIV_MASK = 0x1f << NANDC_DIV_SHIFT, 184*4882a593Smuzhiyun NANDC_PLL_SHIFT = 8, 185*4882a593Smuzhiyun NANDC_PLL_MASK = 3 << NANDC_PLL_SHIFT, 186*4882a593Smuzhiyun NANDC_SEL_APLL = 0, 187*4882a593Smuzhiyun NANDC_SEL_DPLL, 188*4882a593Smuzhiyun NANDC_SEL_GPLL, 189*4882a593Smuzhiyun 190*4882a593Smuzhiyun /* CLKSEL_CON25 */ 191*4882a593Smuzhiyun SPI_PLL_SEL_SHIFT = 8, 192*4882a593Smuzhiyun SPI_PLL_SEL_MASK = 0x3 << SPI_PLL_SEL_SHIFT, 193*4882a593Smuzhiyun SPI_PLL_SEL_APLL = 0, 194*4882a593Smuzhiyun SPI_PLL_SEL_DPLL, 195*4882a593Smuzhiyun SPI_PLL_SEL_GPLL, 196*4882a593Smuzhiyun SPI_DIV_SHIFT = 0, 197*4882a593Smuzhiyun SPI_DIV_MASK = 0x7f << SPI_DIV_SHIFT, 198*4882a593Smuzhiyun 199*4882a593Smuzhiyun /* CRU_CLKSEL28_CON */ 200*4882a593Smuzhiyun LCDC_DCLK_DIV_SHIFT = 8, 201*4882a593Smuzhiyun LCDC_DCLK_DIV_MASK = 0xff << LCDC_DCLK_DIV_SHIFT, 202*4882a593Smuzhiyun LCDC_DCLK_SEL_SHIFT = 0, 203*4882a593Smuzhiyun LCDC_DCLK_SEL_MASK = 0x3 << LCDC_DCLK_SEL_SHIFT, 204*4882a593Smuzhiyun LCDC_DCLK_SEL_APLL = 0, 205*4882a593Smuzhiyun LCDC_DCLK_SEL_DPLL, 206*4882a593Smuzhiyun LCDC_DCLK_SEL_GPLL, 207*4882a593Smuzhiyun 208*4882a593Smuzhiyun /* CRU_CLKSEL31_CON */ 209*4882a593Smuzhiyun LCDC_ACLK_SEL_SHIFT = 14, 210*4882a593Smuzhiyun LCDC_ACLK_SEL_MASK = 0x3 << LCDC_ACLK_SEL_SHIFT, 211*4882a593Smuzhiyun LCDC_ACLK_SEL_APLL = 0, 212*4882a593Smuzhiyun LCDC_ACLK_SEL_DPLL, 213*4882a593Smuzhiyun LCDC_ACLK_SEL_GPLL, 214*4882a593Smuzhiyun LCDC_ACLK_DIV_SHIFT = 8, 215*4882a593Smuzhiyun LCDC_ACLK_DIV_MASK = 0x1f << LCDC_ACLK_DIV_SHIFT, 216*4882a593Smuzhiyun 217*4882a593Smuzhiyun /* CRU_SOFTRST5_CON */ 218*4882a593Smuzhiyun DDRCTRL_PSRST_SHIFT = 11, 219*4882a593Smuzhiyun DDRCTRL_SRST_SHIFT = 10, 220*4882a593Smuzhiyun DDRPHY_PSRST_SHIFT = 9, 221*4882a593Smuzhiyun DDRPHY_SRST_SHIFT = 8, 222*4882a593Smuzhiyun }; 223*4882a593Smuzhiyun #endif 224