1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2016 Heiko Stuebner <heiko@sntech.de> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun #ifndef _ASM_ARCH_CRU_RK3188_H 7*4882a593Smuzhiyun #define _ASM_ARCH_CRU_RK3188_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define OSC_HZ (24 * 1000 * 1000) 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define APLL_HZ (1608 * 1000000) 12*4882a593Smuzhiyun #define APLL_SAFE_HZ (600 * 1000000) 13*4882a593Smuzhiyun #define GPLL_HZ (594 * 1000000) 14*4882a593Smuzhiyun #define CPLL_HZ (384 * 1000000) 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* The SRAM is clocked off aclk_cpu, so we want to max it out for boot speed */ 17*4882a593Smuzhiyun #define CPU_ACLK_HZ 297000000 18*4882a593Smuzhiyun #define CPU_HCLK_HZ 148500000 19*4882a593Smuzhiyun #define CPU_PCLK_HZ 74250000 20*4882a593Smuzhiyun #define CPU_H2P_HZ 74250000 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define PERI_ACLK_HZ 148500000 23*4882a593Smuzhiyun #define PERI_HCLK_HZ 148500000 24*4882a593Smuzhiyun #define PERI_PCLK_HZ 74250000 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* Private data for the clock driver - used by rockchip_get_cru() */ 27*4882a593Smuzhiyun struct rk3188_clk_priv { 28*4882a593Smuzhiyun struct rk3188_grf *grf; 29*4882a593Smuzhiyun struct rk3188_cru *cru; 30*4882a593Smuzhiyun ulong rate; 31*4882a593Smuzhiyun bool has_bwadj; 32*4882a593Smuzhiyun ulong armclk_hz; 33*4882a593Smuzhiyun ulong armclk_enter_hz; 34*4882a593Smuzhiyun ulong armclk_init_hz; 35*4882a593Smuzhiyun bool sync_kernel; 36*4882a593Smuzhiyun bool set_armclk_rate; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun struct rk3188_cru { 40*4882a593Smuzhiyun struct rk3188_pll { 41*4882a593Smuzhiyun u32 con0; 42*4882a593Smuzhiyun u32 con1; 43*4882a593Smuzhiyun u32 con2; 44*4882a593Smuzhiyun u32 con3; 45*4882a593Smuzhiyun } pll[4]; 46*4882a593Smuzhiyun u32 cru_mode_con; 47*4882a593Smuzhiyun u32 cru_clksel_con[35]; 48*4882a593Smuzhiyun u32 cru_clkgate_con[10]; 49*4882a593Smuzhiyun u32 reserved1[2]; 50*4882a593Smuzhiyun u32 cru_glb_srst_fst_value; 51*4882a593Smuzhiyun u32 cru_glb_srst_snd_value; 52*4882a593Smuzhiyun u32 reserved2[2]; 53*4882a593Smuzhiyun u32 cru_softrst_con[9]; 54*4882a593Smuzhiyun u32 cru_misc_con; 55*4882a593Smuzhiyun u32 reserved3[2]; 56*4882a593Smuzhiyun u32 cru_glb_cnt_th; 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun check_member(rk3188_cru, cru_glb_cnt_th, 0x0140); 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun struct rk3188_clk_info { 61*4882a593Smuzhiyun unsigned long id; 62*4882a593Smuzhiyun char *name; 63*4882a593Smuzhiyun bool is_cru; 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun /* CRU_CLKSEL0_CON */ 67*4882a593Smuzhiyun enum { 68*4882a593Smuzhiyun /* a9_core_div: core = core_src / (a9_core_div + 1) */ 69*4882a593Smuzhiyun A9_CORE_DIV_SHIFT = 9, 70*4882a593Smuzhiyun A9_CORE_DIV_MASK = 0x1f, 71*4882a593Smuzhiyun CORE_PLL_SHIFT = 8, 72*4882a593Smuzhiyun CORE_PLL_MASK = 1, 73*4882a593Smuzhiyun CORE_PLL_SELECT_APLL = 0, 74*4882a593Smuzhiyun CORE_PLL_SELECT_GPLL, 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun /* core peri div: core:core_peri = 2:1, 4:1, 8:1 or 16:1 */ 77*4882a593Smuzhiyun CORE_PERI_DIV_SHIFT = 6, 78*4882a593Smuzhiyun CORE_PERI_DIV_MASK = 3, 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun /* aclk_cpu pll selection */ 81*4882a593Smuzhiyun CPU_ACLK_PLL_SHIFT = 5, 82*4882a593Smuzhiyun CPU_ACLK_PLL_MASK = 1, 83*4882a593Smuzhiyun CPU_ACLK_PLL_SELECT_APLL = 0, 84*4882a593Smuzhiyun CPU_ACLK_PLL_SELECT_GPLL, 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun /* a9_cpu_div: aclk_cpu = cpu_src / (a9_cpu_div + 1) */ 87*4882a593Smuzhiyun A9_CPU_DIV_SHIFT = 0, 88*4882a593Smuzhiyun A9_CPU_DIV_MASK = 0x1f, 89*4882a593Smuzhiyun }; 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun /* CRU_CLKSEL1_CON */ 92*4882a593Smuzhiyun enum { 93*4882a593Smuzhiyun /* ahb2apb_pclk_div: hclk_cpu:pclk_cpu = 1:1, 2:1 or 4:1 */ 94*4882a593Smuzhiyun AHB2APB_DIV_SHIFT = 14, 95*4882a593Smuzhiyun AHB2APB_DIV_MASK = 3, 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun /* cpu_pclk_div: aclk_cpu:pclk_cpu = 1:1, 2:1, 4:1 or 8:1 */ 98*4882a593Smuzhiyun CPU_PCLK_DIV_SHIFT = 12, 99*4882a593Smuzhiyun CPU_PCLK_DIV_MASK = 3, 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun /* cpu_hclk_div: aclk_cpu:hclk_cpu = 1:1, 2:1 or 4:1 */ 102*4882a593Smuzhiyun CPU_HCLK_DIV_SHIFT = 8, 103*4882a593Smuzhiyun CPU_HCLK_DIV_MASK = 3, 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun /* core_aclk_div: cire:aclk_core = 1:1, 2:1, 3:1, 4:1 or 8:1 */ 106*4882a593Smuzhiyun CORE_ACLK_DIV_SHIFT = 3, 107*4882a593Smuzhiyun CORE_ACLK_DIV_MASK = 7, 108*4882a593Smuzhiyun }; 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun /* CRU_CLKSEL10_CON */ 111*4882a593Smuzhiyun enum { 112*4882a593Smuzhiyun PERI_SEL_PLL_MASK = 1, 113*4882a593Smuzhiyun PERI_SEL_PLL_SHIFT = 15, 114*4882a593Smuzhiyun PERI_SEL_CPLL = 0, 115*4882a593Smuzhiyun PERI_SEL_GPLL, 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun /* peri pclk div: aclk_bus:pclk_bus = 1:1, 2:1, 4:1 or 8:1 */ 118*4882a593Smuzhiyun PERI_PCLK_DIV_SHIFT = 12, 119*4882a593Smuzhiyun PERI_PCLK_DIV_MASK = 3, 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun /* peripheral bus hclk div:aclk_bus: hclk_bus = 1:1, 2:1 or 4:1 */ 122*4882a593Smuzhiyun PERI_HCLK_DIV_SHIFT = 8, 123*4882a593Smuzhiyun PERI_HCLK_DIV_MASK = 3, 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun /* peri aclk div: aclk_peri = periph_src / (peri_aclk_div + 1) */ 126*4882a593Smuzhiyun PERI_ACLK_DIV_SHIFT = 0, 127*4882a593Smuzhiyun PERI_ACLK_DIV_MASK = 0x1f, 128*4882a593Smuzhiyun }; 129*4882a593Smuzhiyun /* CRU_CLKSEL11_CON */ 130*4882a593Smuzhiyun enum { 131*4882a593Smuzhiyun HSICPHY_DIV_SHIFT = 8, 132*4882a593Smuzhiyun HSICPHY_DIV_MASK = 0x3f, 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun MMC0_DIV_SHIFT = 0, 135*4882a593Smuzhiyun MMC0_DIV_MASK = 0x3f, 136*4882a593Smuzhiyun }; 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun /* CRU_CLKSEL12_CON */ 139*4882a593Smuzhiyun enum { 140*4882a593Smuzhiyun UART_PLL_SHIFT = 15, 141*4882a593Smuzhiyun UART_PLL_MASK = 1, 142*4882a593Smuzhiyun UART_PLL_SELECT_GENERAL = 0, 143*4882a593Smuzhiyun UART_PLL_SELECT_CODEC, 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun EMMC_DIV_SHIFT = 8, 146*4882a593Smuzhiyun EMMC_DIV_MASK = 0x3f, 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun SDIO_DIV_SHIFT = 0, 149*4882a593Smuzhiyun SDIO_DIV_MASK = 0x3f, 150*4882a593Smuzhiyun }; 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun /* CRU_CLKSEL24_CON */ 153*4882a593Smuzhiyun enum { 154*4882a593Smuzhiyun SARADC_DIV_SHIFT = 8, 155*4882a593Smuzhiyun SARADC_DIV_MASK =GENMASK(15, 8), 156*4882a593Smuzhiyun SARADC_DIV_WIDTH = 8, 157*4882a593Smuzhiyun }; 158*4882a593Smuzhiyun 159*4882a593Smuzhiyun /* CRU_CLKSEL25_CON */ 160*4882a593Smuzhiyun enum { 161*4882a593Smuzhiyun SPI1_DIV_SHIFT = 8, 162*4882a593Smuzhiyun SPI1_DIV_MASK = 0x7f, 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun SPI0_DIV_SHIFT = 0, 165*4882a593Smuzhiyun SPI0_DIV_MASK = 0x7f, 166*4882a593Smuzhiyun }; 167*4882a593Smuzhiyun 168*4882a593Smuzhiyun /* CRU_MODE_CON */ 169*4882a593Smuzhiyun enum { 170*4882a593Smuzhiyun GPLL_MODE_SHIFT = 12, 171*4882a593Smuzhiyun GPLL_MODE_MASK = 3, 172*4882a593Smuzhiyun GPLL_MODE_SLOW = 0, 173*4882a593Smuzhiyun GPLL_MODE_NORMAL, 174*4882a593Smuzhiyun GPLL_MODE_DEEP, 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun CPLL_MODE_SHIFT = 8, 177*4882a593Smuzhiyun CPLL_MODE_MASK = 3, 178*4882a593Smuzhiyun CPLL_MODE_SLOW = 0, 179*4882a593Smuzhiyun CPLL_MODE_NORMAL, 180*4882a593Smuzhiyun CPLL_MODE_DEEP, 181*4882a593Smuzhiyun 182*4882a593Smuzhiyun DPLL_MODE_SHIFT = 4, 183*4882a593Smuzhiyun DPLL_MODE_MASK = 3, 184*4882a593Smuzhiyun DPLL_MODE_SLOW = 0, 185*4882a593Smuzhiyun DPLL_MODE_NORMAL, 186*4882a593Smuzhiyun DPLL_MODE_DEEP, 187*4882a593Smuzhiyun 188*4882a593Smuzhiyun APLL_MODE_SHIFT = 0, 189*4882a593Smuzhiyun APLL_MODE_MASK = 3, 190*4882a593Smuzhiyun APLL_MODE_SLOW = 0, 191*4882a593Smuzhiyun APLL_MODE_NORMAL, 192*4882a593Smuzhiyun APLL_MODE_DEEP, 193*4882a593Smuzhiyun }; 194*4882a593Smuzhiyun 195*4882a593Smuzhiyun /* CRU_APLL_CON0 */ 196*4882a593Smuzhiyun enum { 197*4882a593Smuzhiyun CLKR_SHIFT = 8, 198*4882a593Smuzhiyun CLKR_MASK = 0x3f, 199*4882a593Smuzhiyun 200*4882a593Smuzhiyun CLKOD_SHIFT = 0, 201*4882a593Smuzhiyun CLKOD_MASK = 0x3f, 202*4882a593Smuzhiyun }; 203*4882a593Smuzhiyun 204*4882a593Smuzhiyun /* CRU_APLL_CON1 */ 205*4882a593Smuzhiyun enum { 206*4882a593Smuzhiyun CLKF_SHIFT = 0, 207*4882a593Smuzhiyun CLKF_MASK = 0x1fff, 208*4882a593Smuzhiyun }; 209*4882a593Smuzhiyun 210*4882a593Smuzhiyun #endif 211