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Searched refs:CLK_SET_RATE_PARENT (Results 1 – 25 of 280) sorted by relevance

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/OK3568_Linux_fs/kernel/drivers/clk/hisilicon/
H A Dclk-hi3670.c81 CLK_SET_RATE_PARENT, 0x0, 0, 0, },
83 CLK_SET_RATE_PARENT, 0x0, 3, 0, },
85 CLK_SET_RATE_PARENT, 0x0, 27, 0, },
87 CLK_SET_RATE_PARENT, 0x460, 16, 0, },
89 CLK_SET_RATE_PARENT, 0x460, 18, 0, },
91 CLK_SET_RATE_PARENT, 0x460, 20, 0, },
93 CLK_SET_RATE_PARENT, 0x410, 27, 0, },
95 CLK_SET_RATE_PARENT, 0x410, 28, 0, },
97 CLK_SET_RATE_PARENT, 0x410, 26, 0, },
99 CLK_SET_RATE_PARENT, 0x410, 30, 0, },
[all …]
H A Dclk-hi3660.c53 CLK_SET_RATE_PARENT, 0x0, 0, 0, },
55 CLK_SET_RATE_PARENT, 0x0, 21, 0, },
57 CLK_SET_RATE_PARENT, 0x0, 30, 0, },
59 CLK_SET_RATE_PARENT, 0x0, 31, 0, },
61 CLK_SET_RATE_PARENT, 0x10, 0, 0, },
63 CLK_SET_RATE_PARENT, 0x10, 1, 0, },
65 CLK_SET_RATE_PARENT, 0x10, 2, 0, },
67 CLK_SET_RATE_PARENT, 0x10, 3, 0, },
69 CLK_SET_RATE_PARENT, 0x10, 4, 0, },
71 CLK_SET_RATE_PARENT, 0x10, 5, 0, },
[all …]
H A Dclk-hi6220.c55 …{ HI6220_WDT0_PCLK, "wdt0_pclk", "ref32k", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 12,…
56 …{ HI6220_WDT1_PCLK, "wdt1_pclk", "ref32k", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 13,…
57 …{ HI6220_WDT2_PCLK, "wdt2_pclk", "ref32k", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 14,…
58 …{ HI6220_TIMER0_PCLK, "timer0_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 15,…
59 …{ HI6220_TIMER1_PCLK, "timer1_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 16,…
60 …{ HI6220_TIMER2_PCLK, "timer2_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 17,…
61 …{ HI6220_TIMER3_PCLK, "timer3_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 18,…
62 …{ HI6220_TIMER4_PCLK, "timer4_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 19,…
63 …{ HI6220_TIMER5_PCLK, "timer5_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 20,…
64 …{ HI6220_TIMER6_PCLK, "timer6_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 21,…
[all …]
H A Dclk-hi3620.c86 …{ HI3620_TIMER0_MUX, "timer0_mux", timer0_mux_p, ARRAY_SIZE(timer0_mux_p), CLK_SET_RATE_PARENT, 0,…
87 …{ HI3620_TIMER1_MUX, "timer1_mux", timer1_mux_p, ARRAY_SIZE(timer1_mux_p), CLK_SET_RATE_PARENT, 0,…
88 …{ HI3620_TIMER2_MUX, "timer2_mux", timer2_mux_p, ARRAY_SIZE(timer2_mux_p), CLK_SET_RATE_PARENT, 0,…
89 …{ HI3620_TIMER3_MUX, "timer3_mux", timer3_mux_p, ARRAY_SIZE(timer3_mux_p), CLK_SET_RATE_PARENT, 0,…
90 …{ HI3620_TIMER4_MUX, "timer4_mux", timer4_mux_p, ARRAY_SIZE(timer4_mux_p), CLK_SET_RATE_PARENT, 0x…
91 …{ HI3620_TIMER5_MUX, "timer5_mux", timer5_mux_p, ARRAY_SIZE(timer5_mux_p), CLK_SET_RATE_PARENT, 0x…
92 …{ HI3620_TIMER6_MUX, "timer6_mux", timer6_mux_p, ARRAY_SIZE(timer6_mux_p), CLK_SET_RATE_PARENT, 0x…
93 …{ HI3620_TIMER7_MUX, "timer7_mux", timer7_mux_p, ARRAY_SIZE(timer7_mux_p), CLK_SET_RATE_PARENT, 0x…
94 …{ HI3620_TIMER8_MUX, "timer8_mux", timer8_mux_p, ARRAY_SIZE(timer8_mux_p), CLK_SET_RATE_PARENT, 0x…
95 …{ HI3620_TIMER9_MUX, "timer9_mux", timer9_mux_p, ARRAY_SIZE(timer9_mux_p), CLK_SET_RATE_PARENT, 0x…
[all …]
H A Dcrg-hi3798cv200.c76 CLK_SET_RATE_PARENT, 0xa0, 8, 3, 0, mmc_mux_table, },
79 CLK_SET_RATE_PARENT, 0x188, 2, 2, 0, comphy_mux_table, },
82 CLK_SET_RATE_PARENT, 0x188, 10, 2, 0, comphy_mux_table, },
84 ARRAY_SIZE(sdio_mux_p), CLK_SET_RATE_PARENT,
93 CLK_SET_RATE_PARENT, 0xa0, 12, 3, mmc_phase_degrees,
96 CLK_SET_RATE_PARENT, 0xa0, 16, 3, mmc_phase_degrees,
103 CLK_SET_RATE_PARENT, 0x68, 4, 0, },
106 CLK_SET_RATE_PARENT, 0x6C, 4, 0, },
108 CLK_SET_RATE_PARENT, 0x6C, 8, 0, },
110 CLK_SET_RATE_PARENT, 0x6C, 12, 0, },
[all …]
H A Dclk-hix5hd2.c60 CLK_SET_RATE_PARENT, 0x5c, 8, 3, 0, sfc_mux_table, },
62 CLK_SET_RATE_PARENT, 0xa0, 8, 2, 0, sdio_mux_table, },
64 CLK_SET_RATE_PARENT, 0x9c, 8, 2, 0, sdio_mux_table, },
67 CLK_SET_RATE_PARENT, 0x120, 8, 2, 0, fephy_mux_table, },
73 CLK_SET_RATE_PARENT, 0x5c, 0, 0, },
75 CLK_SET_RATE_PARENT, 0x5c, 4, CLK_GATE_SET_TO_DISABLE, },
78 CLK_SET_RATE_PARENT, 0x9c, 0, 0, },
80 CLK_SET_RATE_PARENT, 0x9c, 1, 0, },
82 CLK_SET_RATE_PARENT, 0x9c, 4, CLK_GATE_SET_TO_DISABLE, },
85 CLK_SET_RATE_PARENT, 0xa0, 0, 0, },
[all …]
H A Dcrg-hi3516cv300.c70 CLK_SET_RATE_PARENT, 0xe4, 19, 1, 0, uart_mux_table, },
72 CLK_SET_RATE_PARENT, 0xc0, 2, 3, 0, fmc_mux_table, },
74 CLK_SET_RATE_PARENT, 0xc4, 4, 2, 0, mmc_mux_table, },
76 CLK_SET_RATE_PARENT, 0xc4, 12, 2, 0, mmc_mux_table, },
78 CLK_SET_RATE_PARENT, 0xc4, 20, 2, 0, mmc2_mux_table, },
80 CLK_SET_RATE_PARENT, 0xc8, 4, 2, 0, mmc_mux_table, },
82 CLK_SET_RATE_PARENT, 0x38, 2, 2, 0, pwm_mux_table, },
87 { HI3516CV300_UART0_CLK, "clk_uart0", "uart_mux", CLK_SET_RATE_PARENT,
89 { HI3516CV300_UART1_CLK, "clk_uart1", "uart_mux", CLK_SET_RATE_PARENT,
91 { HI3516CV300_UART2_CLK, "clk_uart2", "uart_mux", CLK_SET_RATE_PARENT,
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/mmp/
H A Dclk-of-mmp2.c176 …{MMP2_CLK_I2S0, "i2s0_clk", "i2s0_pll", CLK_SET_RATE_PARENT, MPMU_ACGR, 0x200000, 0x200000, 0x0, 0…
177 …{MMP2_CLK_I2S1, "i2s1_clk", "i2s1_pll", CLK_SET_RATE_PARENT, MPMU_ACGR, 0x100000, 0x100000, 0x0, 0…
202 CLK_SET_RATE_PARENT, in mmp2_main_clk_init()
209 CLK_SET_RATE_PARENT, in mmp2_main_clk_init()
214 CLK_SET_RATE_PARENT, in mmp2_main_clk_init()
240 …{0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0…
241 …{0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART1…
242 …{0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART2…
243 …{0, "uart3_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART3…
244 …{0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP0, 4,…
[all …]
H A Dclk-of-pxa168.c106 CLK_SET_RATE_PARENT, in pxa168_pll_init()
131 …{0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0…
132 …{0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART1…
133 …{0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART2…
134 …{0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP0, 4,…
135 …{0, "ssp1_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP1, 4,…
136 …{0, "ssp2_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP2, 4,…
137 …{0, "ssp3_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP3, 4,…
138 …{0, "ssp4_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP4, 4,…
139 …{0, "timer_mux", timer_parent_names, ARRAY_SIZE(timer_parent_names), CLK_SET_RATE_PARENT, APBC_TIM…
[all …]
H A Dclk-of-pxa910.c106 CLK_SET_RATE_PARENT, in pxa910_pll_init()
129 …{0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0…
130 …{0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART1…
131 …{0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP0, 4,…
132 …{0, "ssp1_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP1, 4,…
133 …{0, "timer0_mux", timer_parent_names, ARRAY_SIZE(timer_parent_names), CLK_SET_RATE_PARENT, APBC_TI…
134 …{0, "timer1_mux", timer_parent_names, ARRAY_SIZE(timer_parent_names), CLK_SET_RATE_PARENT, APBC_TI…
138 …{0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBCP_UART…
142 …{PXA910_CLK_TWSI0, "twsi0_clk", "pll1_13_1_5", CLK_SET_RATE_PARENT, APBC_TWSI0, 0x3, 0x3, 0x0, 0, …
143 …{PXA910_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_GPIO, 0x3, 0x3, 0x0, 0, &reset_l…
[all …]
H A Dclk-of-pxa1928.c80 CLK_SET_RATE_PARENT, in pxa1928_pll_init()
99 …{0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, PXA1928_CL…
100 …{0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, PXA1928_CL…
101 …{0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, PXA1928_CL…
102 …{0, "uart3_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, PXA1928_CL…
103 …{0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, PXA1928_CLK_S…
104 …{0, "ssp1_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, PXA1928_CLK_S…
108 …{PXA1928_CLK_TWSI0, "twsi0_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI0 * 4, 0x3, 0x3, 0…
109 …{PXA1928_CLK_TWSI1, "twsi1_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI1 * 4, 0x3, 0x3, 0…
110 …{PXA1928_CLK_TWSI2, "twsi2_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI2 * 4, 0x3, 0x3, 0…
[all …]
H A Dclk-mmp2.c119 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
123 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
127 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
131 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
135 CLK_SET_RATE_PARENT, 1, 5); in mmp2_clk_init()
139 CLK_SET_RATE_PARENT, 1, 3); in mmp2_clk_init()
143 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
147 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
151 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
155 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
[all …]
H A Dclk-pxa168.c106 CLK_SET_RATE_PARENT, 1, 2); in pxa168_clk_init()
110 CLK_SET_RATE_PARENT, 1, 2); in pxa168_clk_init()
114 CLK_SET_RATE_PARENT, 1, 2); in pxa168_clk_init()
118 CLK_SET_RATE_PARENT, 1, 2); in pxa168_clk_init()
122 CLK_SET_RATE_PARENT, 1, 3); in pxa168_clk_init()
126 CLK_SET_RATE_PARENT, 1, 2); in pxa168_clk_init()
130 CLK_SET_RATE_PARENT, 1, 2); in pxa168_clk_init()
134 CLK_SET_RATE_PARENT, 1, 2); in pxa168_clk_init()
138 CLK_SET_RATE_PARENT, 1, 2); in pxa168_clk_init()
142 CLK_SET_RATE_PARENT, 1, 13); in pxa168_clk_init()
[all …]
H A Dclk-pxa910.c111 CLK_SET_RATE_PARENT, 1, 2); in pxa910_clk_init()
115 CLK_SET_RATE_PARENT, 1, 2); in pxa910_clk_init()
119 CLK_SET_RATE_PARENT, 1, 2); in pxa910_clk_init()
123 CLK_SET_RATE_PARENT, 1, 2); in pxa910_clk_init()
127 CLK_SET_RATE_PARENT, 1, 3); in pxa910_clk_init()
131 CLK_SET_RATE_PARENT, 1, 2); in pxa910_clk_init()
135 CLK_SET_RATE_PARENT, 1, 2); in pxa910_clk_init()
139 CLK_SET_RATE_PARENT, 1, 2); in pxa910_clk_init()
143 CLK_SET_RATE_PARENT, 1, 2); in pxa910_clk_init()
147 CLK_SET_RATE_PARENT, 1, 13); in pxa910_clk_init()
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/zte/
H A Dclk-zx296718.c399 FFACTOR(0, "clk1600m", "pll_cpu", 1, 1, CLK_SET_RATE_PARENT),
400 FFACTOR(0, "clk800m", "pll_cpu", 1, 2, CLK_SET_RATE_PARENT),
433 FFACTOR(0, "clk_vga", "pll_vga", 1, 1, CLK_SET_RATE_PARENT),
448 FFACTOR(0, "emmc_mux_div2", "emmc_mux", 1, 2, CLK_SET_RATE_PARENT),
464 MUX_F(0, "a53_mux", a53_coreclk_p, TOP_CLK_MUX0, 0, 3, CLK_SET_RATE_PARENT, 0),
473 MUX_F(0, "wdt_mux", wdt_ares_p, TOP_CLK_MUX9, 8, 1, CLK_SET_RATE_PARENT, 0),
482 MUX_F(0, "vou_main_w_mux", vou_main_wclk_p, TOP_CLK_MUX7, 4, 3, CLK_SET_RATE_PARENT, 0),
483 MUX_F(0, "vou_aux_w_mux", vou_aux_wclk_p, TOP_CLK_MUX7, 8, 3, CLK_SET_RATE_PARENT, 0),
494 …GATE(CPU_DBG_GATE, "dbg_wclk", "dbg_mux", TOP_CLK_GATE0, 4, CLK_SET_RATE_PARENT, …
495 …GATE(A72_GATE, "a72_coreclk", "a72_mux", TOP_CLK_GATE0, 3, CLK_SET_RATE_PARENT, …
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/rockchip/
H A Drockchip_vop2_clk.c95 MUX("port0_dclk_src", mux_port0_dclk_src_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT),
96 DIV("dclk_core0", "port0_dclk_src", CLK_SET_RATE_PARENT, 2),
97 DIV("dclk_out0", "port0_dclk_src", CLK_SET_RATE_PARENT, 2),
99 FACTOR("port1_dclk_src", "dclk1", CLK_SET_RATE_PARENT),
100 DIV("dclk_core1", "port1_dclk_src", CLK_SET_RATE_PARENT, 2),
101 DIV("dclk_out1", "port1_dclk_src", CLK_SET_RATE_PARENT, 2),
103 MUX("port2_dclk_src", mux_port2_dclk_src_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT),
104 DIV("dclk_core2", "port2_dclk_src", CLK_SET_RATE_PARENT, 2),
105 DIV("dclk_out2", "port2_dclk_src", CLK_SET_RATE_PARENT, 2),
107 FACTOR("port3_dclk_src", "dclk3", CLK_SET_RATE_PARENT),
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/qcom/
H A Dgcc-ipq8074.c421 .flags = CLK_SET_RATE_PARENT,
468 .flags = CLK_SET_RATE_PARENT,
501 .flags = CLK_SET_RATE_PARENT,
535 .flags = CLK_SET_RATE_PARENT,
549 .flags = CLK_SET_RATE_PARENT,
582 .flags = CLK_SET_RATE_PARENT,
614 .flags = CLK_SET_RATE_PARENT,
649 .flags = CLK_SET_RATE_PARENT,
1008 .flags = CLK_SET_RATE_PARENT,
1051 .flags = CLK_SET_RATE_PARENT,
[all …]
H A Dmmcc-msm8996.c284 .flags = CLK_SET_RATE_PARENT,
314 .flags = CLK_SET_RATE_PARENT,
340 .flags = CLK_SET_RATE_PARENT,
366 .flags = CLK_SET_RATE_PARENT,
392 .flags = CLK_SET_RATE_PARENT,
418 .flags = CLK_SET_RATE_PARENT,
444 .flags = CLK_SET_RATE_PARENT,
470 .flags = CLK_SET_RATE_PARENT,
540 .flags = CLK_SET_RATE_PARENT,
653 .flags = CLK_SET_RATE_PARENT,
[all …]
H A Dmmcc-apq8084.c575 .flags = CLK_SET_RATE_PARENT,
589 .flags = CLK_SET_RATE_PARENT,
840 .flags = CLK_SET_RATE_PARENT,
853 .flags = CLK_SET_RATE_PARENT,
891 .flags = CLK_SET_RATE_PARENT,
960 .flags = CLK_SET_RATE_PARENT,
1109 .flags = CLK_SET_RATE_PARENT,
1126 .flags = CLK_SET_RATE_PARENT,
1143 .flags = CLK_SET_RATE_PARENT,
1160 .flags = CLK_SET_RATE_PARENT,
[all …]
H A Dgcc-msm8996.c228 .flags = CLK_SET_RATE_PARENT,
243 .flags = CLK_SET_RATE_PARENT,
1279 .flags = CLK_SET_RATE_PARENT,
1294 .flags = CLK_SET_RATE_PARENT,
1309 .flags = CLK_SET_RATE_PARENT,
1324 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1337 .flags = CLK_SET_RATE_PARENT,
1352 .flags = CLK_SET_RATE_PARENT,
1367 .flags = CLK_SET_RATE_PARENT,
1382 .flags = CLK_SET_RATE_PARENT,
[all …]
H A Dgcc-sm8150.c245 .flags = CLK_SET_RATE_PARENT,
268 .flags = CLK_SET_RATE_PARENT,
294 .flags = CLK_SET_RATE_PARENT,
318 .flags = CLK_SET_RATE_PARENT,
333 .flags = CLK_SET_RATE_PARENT,
348 .flags = CLK_SET_RATE_PARENT,
369 .flags = CLK_SET_RATE_PARENT,
384 .flags = CLK_SET_RATE_PARENT,
405 .flags = CLK_SET_RATE_PARENT,
427 .flags = CLK_SET_RATE_PARENT,
[all …]
H A Dgcc-ipq6018.c78 .flags = CLK_SET_RATE_PARENT,
92 .flags = CLK_SET_RATE_PARENT,
136 .flags = CLK_SET_RATE_PARENT,
167 .flags = CLK_SET_RATE_PARENT,
198 .flags = CLK_SET_RATE_PARENT,
249 .flags = CLK_SET_RATE_PARENT,
280 .flags = CLK_SET_RATE_PARENT,
359 .flags = CLK_SET_RATE_PARENT,
412 .flags = CLK_SET_RATE_PARENT,
713 .flags = CLK_SET_RATE_PARENT,
[all …]
H A Dgcc-msm8916.c986 .flags = CLK_SET_RATE_PARENT,
1043 .flags = CLK_SET_RATE_PARENT,
1232 .flags = CLK_SET_RATE_PARENT,
1249 .flags = CLK_SET_RATE_PARENT,
1311 .flags = CLK_SET_RATE_PARENT,
1342 .flags = CLK_SET_RATE_PARENT,
1373 .flags = CLK_SET_RATE_PARENT,
1408 .flags = CLK_SET_RATE_PARENT,
1425 .flags = CLK_SET_RATE_PARENT,
1464 .flags = CLK_SET_RATE_PARENT,
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/rockchip/
H A Dclk-rk3308.c203 MUX(0, "clk_uart0_mux", mux_uart0_p, CLK_SET_RATE_PARENT,
207 MUX(0, "clk_uart1_mux", mux_uart1_p, CLK_SET_RATE_PARENT,
211 MUX(0, "clk_uart2_mux", mux_uart2_p, CLK_SET_RATE_PARENT,
215 MUX(0, "clk_uart3_mux", mux_uart3_p, CLK_SET_RATE_PARENT,
219 MUX(0, "clk_uart4_mux", mux_uart4_p, CLK_SET_RATE_PARENT,
223 MUX(0, "dclk_vop_mux", mux_dclk_vop_p, CLK_SET_RATE_PARENT,
227 MUX(SCLK_RTC32K, "clk_rtc32k", mux_rtc32k_p, CLK_SET_RATE_PARENT,
231 MUX(0, "clk_pdm_mux", mux_pdm_p, CLK_SET_RATE_PARENT,
235 MUX(SCLK_I2S0_8CH_TX_MUX, "clk_i2s0_8ch_tx_mux", mux_i2s0_8ch_tx_p, CLK_SET_RATE_PARENT,
239 MUX(SCLK_I2S0_8CH_RX_MUX, "clk_i2s0_8ch_rx_mux", mux_i2s0_8ch_rx_p, CLK_SET_RATE_PARENT,
[all …]
H A Dclk-px30.c214 MUX(0, "clk_pdm_mux", mux_pdm_p, CLK_SET_RATE_PARENT,
218 MUX(SCLK_I2S0_TX_MUX, "clk_i2s0_tx_mux", mux_i2s0_tx_p, CLK_SET_RATE_PARENT,
222 MUX(SCLK_I2S0_RX_MUX, "clk_i2s0_rx_mux", mux_i2s0_rx_p, CLK_SET_RATE_PARENT,
226 MUX(0, "clk_i2s1_mux", mux_i2s1_p, CLK_SET_RATE_PARENT,
230 MUX(0, "clk_i2s2_mux", mux_i2s2_p, CLK_SET_RATE_PARENT,
234 MUX(0, "clk_uart1_mux", mux_uart1_p, CLK_SET_RATE_PARENT,
238 MUX(0, "clk_uart2_mux", mux_uart2_p, CLK_SET_RATE_PARENT,
242 MUX(0, "clk_uart3_mux", mux_uart3_p, CLK_SET_RATE_PARENT,
246 MUX(0, "clk_uart4_mux", mux_uart4_p, CLK_SET_RATE_PARENT,
250 MUX(0, "clk_uart5_mux", mux_uart5_p, CLK_SET_RATE_PARENT,
[all …]

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