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Searched refs:uint32_t (Results 1 – 25 of 786) sorted by relevance

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/rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/
H A Dioc_rv1126b.h13 uint32_t gpio0a_iomux_sel_0; /* address offset: 0x0000 */
14 uint32_t gpio0a_iomux_sel_1; /* address offset: 0x0004 */
15 uint32_t gpio0b_iomux_sel_0; /* address offset: 0x0008 */
16 uint32_t gpio0b_iomux_sel_1; /* address offset: 0x000c */
17 uint32_t reserved0010[60]; /* address offset: 0x0010 */
18 uint32_t gpio0a_ds_0; /* address offset: 0x0100 */
19 uint32_t gpio0a_ds_1; /* address offset: 0x0104 */
20 uint32_t gpio0a_ds_2; /* address offset: 0x0108 */
21 uint32_t gpio0a_ds_3; /* address offset: 0x010c */
22 uint32_t gpio0b_ds_0; /* address offset: 0x0110 */
[all …]
H A Dioc_rk3562.h12 uint32_t gpio1a_iomux_sel_l; /* Address Offset: 0x0000 */
13 uint32_t gpio1a_iomux_sel_h; /* Address Offset: 0x0004 */
14 uint32_t gpio1b_iomux_sel_l; /* Address Offset: 0x0008 */
15 uint32_t gpio1b_iomux_sel_h; /* Address Offset: 0x000C */
16 uint32_t gpio1c_iomux_sel_l; /* Address Offset: 0x0010 */
17 uint32_t gpio1c_iomux_sel_h; /* Address Offset: 0x0014 */
18 uint32_t gpio1d_iomux_sel_l; /* Address Offset: 0x0018 */
19 uint32_t gpio1d_iomux_sel_h; /* Address Offset: 0x001C */
20 uint32_t gpio2a_iomux_sel_l; /* Address Offset: 0x0020 */
21 uint32_t reserved0024[23]; /* Address Offset: 0x0024 */
[all …]
H A Dgrf_rk3506.h13 uint32_t soc_con0; /* address offset: 0x0000 */
14 uint32_t soc_con1; /* address offset: 0x0004 */
15 uint32_t soc_con2; /* address offset: 0x0008 */
16 uint32_t soc_con3; /* address offset: 0x000c */
17 uint32_t soc_con4; /* address offset: 0x0010 */
18 uint32_t soc_con5; /* address offset: 0x0014 */
19 uint32_t soc_con6; /* address offset: 0x0018 */
20 uint32_t soc_con7; /* address offset: 0x001c */
21 uint32_t soc_con8; /* address offset: 0x0020 */
22 uint32_t soc_con9; /* address offset: 0x0024 */
[all …]
H A Dgrf_rv1126b.h13 uint32_t con0; /* address offset: 0x0000 */
14 uint32_t con1; /* address offset: 0x0004 */
15 uint32_t mem_cfg_uhdspra; /* address offset: 0x0008 */
16 uint32_t status0; /* address offset: 0x000c */
17 uint32_t status1; /* address offset: 0x0010 */
24 uint32_t con0; /* address offset: 0x0000 */
25 uint32_t con1; /* address offset: 0x0004 */
26 uint32_t reserved0008[2]; /* address offset: 0x0008 */
27 uint32_t con4; /* address offset: 0x0010 */
28 uint32_t reserved0014[7]; /* address offset: 0x0014 */
[all …]
H A Dioc_rk3576.h13 uint32_t gpio0a_iomux_sel_l; /* address offset: 0x0000 */
14 uint32_t gpio0a_iomux_sel_h; /* address offset: 0x0004 */
15 uint32_t gpio0b_iomux_sel_l; /* address offset: 0x0008 */
16 uint32_t reserved000c; /* address offset: 0x000c */
17 uint32_t gpio0a_ds_l; /* address offset: 0x0010 */
18 uint32_t gpio0a_ds_h; /* address offset: 0x0014 */
19 uint32_t gpio0b_ds_l; /* address offset: 0x0018 */
20 uint32_t reserved001c; /* address offset: 0x001c */
21 uint32_t gpio0a_pull; /* address offset: 0x0020 */
22 uint32_t gpio0b_pull_l; /* address offset: 0x0024 */
[all …]
H A Dgrf_rk3588.h12 uint32_t wdt_con0; /* Address Offset: 0x0000 */
13 uint32_t reserved0004[3]; /* Address Offset: 0x0004 */
14 uint32_t uart_con0; /* Address Offset: 0x0010 */
15 uint32_t uart_con1; /* Address Offset: 0x0014 */
16 uint32_t reserved0018[42]; /* Address Offset: 0x0018 */
17 uint32_t gic_con0; /* Address Offset: 0x00C0 */
18 uint32_t reserved00c4[79]; /* Address Offset: 0x00C4 */
19 uint32_t memcfg_con0; /* Address Offset: 0x0200 */
20 uint32_t memcfg_con1; /* Address Offset: 0x0204 */
21 uint32_t memcfg_con2; /* Address Offset: 0x0208 */
[all …]
H A Dgrf_rk3576.h13 uint32_t reserved0000[11]; /* address offset: 0x0000 */
14 uint32_t cpu_status[1]; /* address offset: 0x002c */
15 uint32_t reserved0030; /* address offset: 0x0030 */
16 uint32_t cpu_con[2]; /* address offset: 0x0034 */
17 uint32_t cpu_mem_cfg_hdsprf; /* address offset: 0x003c */
18 uint32_t reserved0040; /* address offset: 0x0040 */
19 uint32_t cpu_mem_cfg_hssprf; /* address offset: 0x0044 */
26 uint32_t cci_con[5]; /* address offset: 0x0000 */
27 uint32_t reserved0014[8]; /* address offset: 0x0014 */
28 uint32_t cci_status[5]; /* address offset: 0x0034 */
[all …]
H A Dioc_rk3506.h13 uint32_t gpio0a_iomux_sel_0; /* address offset: 0x0000 */
14 uint32_t gpio0a_iomux_sel_1; /* address offset: 0x0004 */
15 uint32_t gpio0b_iomux_sel_0; /* address offset: 0x0008 */
16 uint32_t gpio0b_iomux_sel_1; /* address offset: 0x000c */
17 uint32_t gpio0c_iomux_sel_0; /* address offset: 0x0010 */
18 uint32_t gpio0c_iomux_sel_1; /* address offset: 0x0014 */
19 uint32_t reserved0018[58]; /* address offset: 0x0018 */
20 uint32_t gpio0a_ds_0; /* address offset: 0x0100 */
21 uint32_t gpio0a_ds_1; /* address offset: 0x0104 */
22 uint32_t gpio0a_ds_2; /* address offset: 0x0108 */
[all …]
H A Dioc_rv1103b.h13 uint32_t gpio0a_iomux_sel_0; /* address offset: 0x0000 */
14 uint32_t gpio0a_iomux_sel_1; /* address offset: 0x0004 */
15 uint32_t reserved0008[62]; /* address offset: 0x0008 */
16 uint32_t gpio0a_ds_0; /* address offset: 0x0100 */
17 uint32_t gpio0a_ds_1; /* address offset: 0x0104 */
18 uint32_t gpio0a_ds_2; /* address offset: 0x0108 */
19 uint32_t gpio0a_ds_3; /* address offset: 0x010c */
20 uint32_t reserved0110[60]; /* address offset: 0x0110 */
21 uint32_t gpio0a_pull; /* address offset: 0x0200 */
22 uint32_t reserved0204[63]; /* address offset: 0x0204 */
[all …]
H A Dioc_rk3528.h12 uint32_t gpio0a_iomux_sel_l; /* Address Offset: 0x0000 */
13 uint32_t gpio0a_iomux_sel_h; /* Address Offset: 0x0004 */
14 uint32_t reserved0008[62]; /* Address Offset: 0x0008 */
15 uint32_t gpio0a_ds[3]; /* Address Offset: 0x0100 */
16 uint32_t reserved010c[61]; /* Address Offset: 0x010C */
17 uint32_t gpio0a_pull; /* Address Offset: 0x0200 */
18 uint32_t reserved0204[63]; /* Address Offset: 0x0204 */
19 uint32_t gpio0a_ie; /* Address Offset: 0x0300 */
20 uint32_t reserved0304[63]; /* Address Offset: 0x0304 */
21 uint32_t gpio0a_smt; /* Address Offset: 0x0400 */
[all …]
H A Dgrf_rv1103b.h24 uint32_t reserved0[(SYS_GRF + 0xA0 - VEPU_GRF)/ 4];
25 uint32_t gmac_con0; /* address offset: 0x00a0 */
26 uint32_t gmac_clk_con; /* address offset: 0x00a4 */
27 uint32_t gmac_st; /* address offset: 0x00a8 */
28 uint32_t reserved00ac; /* address offset: 0x00ac */
29 uint32_t macphy_con0; /* address offset: 0x00b0 */
30 uint32_t macphy_con1; /* address offset: 0x00b4 */
31 uint32_t reserved1[(PMU_GRF + 0x10000 - (SYS_GRF + 0xB4)) / 4];
38 uint32_t con0; /* address offset: 0x0000 */
39 uint32_t mem_cfg_uhdspra; /* address offset: 0x0004 */
[all …]
H A Dioc_rk3588.h12 uint32_t reserved0000[3]; /* Address Offset: 0x0000 */
13 uint32_t gpio0b_iomux_sel_h; /* Address Offset: 0x000C */
14 uint32_t gpio0c_iomux_sel_l; /* Address Offset: 0x0010 */
15 uint32_t gpio0c_iomux_sel_h; /* Address Offset: 0x0014 */
16 uint32_t gpio0d_iomux_sel_l; /* Address Offset: 0x0018 */
17 uint32_t gpio0d_iomux_sel_h; /* Address Offset: 0x001C */
18 uint32_t gpio1a_iomux_sel_l; /* Address Offset: 0x0020 */
19 uint32_t gpio1a_iomux_sel_h; /* Address Offset: 0x0024 */
20 uint32_t gpio1b_iomux_sel_l; /* Address Offset: 0x0028 */
21 uint32_t gpio1b_iomux_sel_h; /* Address Offset: 0x002C */
[all …]
H A Dgrf_rk3528.h12 uint32_t reserved0[0x40018 / 4];
15 uint32_t gmac1_con0; /* Address Offset: 0x40018 */
16 uint32_t gmac1_con1; /* Address Offset: 0x4001c */
17 uint32_t reserved1[(0x60018 - 0x4001c) / 4 - 1];
20 uint32_t gmac0_con; /* Address Offset: 0x60018 */
21 uint32_t macphy_con0; /* Address Offset: 0x6001c */
22 uint32_t macphy_con1; /* Address Offset: 0x60020 */
23 uint32_t sdmmc_con0; /* Address Offset: 0x60024 */
24 uint32_t sdmmc_con1; /* Address Offset: 0x60028 */
25 uint32_t reserved2[(0x70000 - 0x60028) / 4 - 1];
[all …]
H A Dgrf_rk3562.h13 uint32_t reserved1[(0x0100 - 0x0000) / 4]; /* address offset: 0x0000 */
14 uint32_t soc_con[13]; /* address offset: 0x0100 */
15 uint32_t soc_status[1]; /* address offset: 0x0134 */
16 uint32_t reserved2[(0x0180 - 0x0134) / 4 - 1]; /* address offset: 0x0138 */
17 uint32_t pvtm_con[1]; /* address offset: 0x0180 */
18 uint32_t reserved3[(0x0200 - 0x0180) / 4 - 1]; /* address offset: 0x0184 */
19 uint32_t os_reg[12]; /* address offset: 0x0200 */
20 uint32_t reset_function_status; /* address offset: 0x0230 */
21 uint32_t reset_function_clr; /* address offset: 0x0234 */
22 uint32_t reserved4[(0x0380 - 0x0234) / 4 - 1]; /* address offset: 0x0238 */
[all …]
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-mxs/
H A Dregs-digctl.h22 uint32_t hw_digctl_writeonce; /* 0x060 */
23 uint32_t reserved_writeonce[3];
26 uint32_t hw_digctl_entropy; /* 0x090 */
27 uint32_t reserved_entropy[3];
28 uint32_t hw_digctl_entropy_latched; /* 0x0a0 */
29 uint32_t reserved_entropy_latched[3];
31 uint32_t reserved1[4];
34 uint32_t hw_digctl_dbgrd; /* 0x0d0 */
35 uint32_t reserved_hw_digctl_dbgrd[3];
36 uint32_t hw_digctl_dbg; /* 0x0e0 */
[all …]
H A Dregs-usb.h14 uint32_t hw_usbctrl_id; /* 0x000 */
15 uint32_t hw_usbctrl_hwgeneral; /* 0x004 */
16 uint32_t hw_usbctrl_hwhost; /* 0x008 */
17 uint32_t hw_usbctrl_hwdevice; /* 0x00c */
18 uint32_t hw_usbctrl_hwtxbuf; /* 0x010 */
19 uint32_t hw_usbctrl_hwrxbuf; /* 0x014 */
21 uint32_t reserved1[26];
23 uint32_t hw_usbctrl_gptimer0ld; /* 0x080 */
24 uint32_t hw_usbctrl_gptimer0ctrl; /* 0x084 */
25 uint32_t hw_usbctrl_gptimer1ld; /* 0x088 */
[all …]
/rk3399_rockchip-uboot/drivers/net/
H A Dfec_mxc.h25 uint32_t res0[1]; /* MBAR_ETH + 0x000 */
26 uint32_t ievent; /* MBAR_ETH + 0x004 */
27 uint32_t imask; /* MBAR_ETH + 0x008 */
29 uint32_t res1[1]; /* MBAR_ETH + 0x00C */
30 uint32_t r_des_active; /* MBAR_ETH + 0x010 */
31 uint32_t x_des_active; /* MBAR_ETH + 0x014 */
32 uint32_t res2[3]; /* MBAR_ETH + 0x018-20 */
33 uint32_t ecntrl; /* MBAR_ETH + 0x024 */
35 uint32_t res3[6]; /* MBAR_ETH + 0x028-03C */
36 uint32_t mii_data; /* MBAR_ETH + 0x040 */
[all …]
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-ep93xx/
H A Dep93xx.h36 uint32_t control;
37 uint32_t interrupt;
38 uint32_t ppalloc;
39 uint32_t status;
40 uint32_t reserved0;
41 uint32_t remain;
42 uint32_t reserved1[2];
43 uint32_t maxcnt0;
44 uint32_t base0;
45 uint32_t current0;
[all …]
/rk3399_rockchip-uboot/include/optee_include/
H A DOpteeClientInterface.h63 uint32_t algo;
64 uint32_t mode;
65 uint32_t operation;
67 uint32_t key_len;
86 uint32_t trusty_read_rollback_index(uint32_t slot, uint64_t *value);
87 uint32_t trusty_write_rollback_index(uint32_t slot, uint64_t value);
88 uint32_t trusty_read_permanent_attributes(uint8_t *attributes, uint32_t size);
89 uint32_t trusty_write_permanent_attributes(uint8_t *attributes, uint32_t size);
90 uint32_t trusty_read_permanent_attributes_cer(uint8_t *attributes,
91 uint32_t size);
[all …]
H A Dtee_api_types.h20 typedef uint32_t TEE_Result;
23 uint32_t timeLow;
35 uint32_t login;
52 uint32_t size;
55 uint32_t a;
56 uint32_t b;
81 typedef uint32_t TEE_ObjectType;
84 uint32_t objectType;
85 uint32_t keySize;
86 uint32_t maxKeySize;
[all …]
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-mx7ulp/
H A Dimx_lpi2c.h92 #define LPI2C_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATUR…
95 #define LPI2C_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_…
98 #define LPI2C_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_…
103 #define LPI2C_PARAM_MTXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIF…
106 #define LPI2C_PARAM_MRXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIF…
111 #define LPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIF…
114 #define LPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIF…
117 #define LPI2C_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SH…
120 #define LPI2C_MCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SH…
123 #define LPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIF…
[all …]
/rk3399_rockchip-uboot/include/rockchip/
H A Drkce_core.h136 uint32_t aes_ver;
137 uint32_t des_ver;
138 uint32_t sm4_ver;
139 uint32_t hash_ver;
140 uint32_t hmac_ver;
141 uint32_t pka_ver;
142 uint32_t extra_feature;
143 uint32_t ce_ver;
147 uint32_t pc_len_l;
148 uint32_t pc_len_h;
[all …]
H A Drkce_reg.h17 uint32_t CLK_CTL; /* Address Offset: 0x0000 */
18 uint32_t RST_CTL; /* Address Offset: 0x0004 */
19 uint32_t RESERVED0008[126]; /* Address Offset: 0x0008 */
20 uint32_t TD_ADDR; /* Address Offset: 0x0200 */
21 uint32_t TD_LOAD_CTRL; /* Address Offset: 0x0204 */
22 uint32_t FIFO_ST; /* Address Offset: 0x0208 */
23 uint32_t RESERVED020C; /* Address Offset: 0x020C */
24 uint32_t SYMM_INT_EN; /* Address Offset: 0x0210 */
25 uint32_t SYMM_INT_ST; /* Address Offset: 0x0214 */
26 uint32_t SYMM_TD_ID; /* Address Offset: 0x0218 */
[all …]
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-pxa/
H A Dregs-usb.h14 uint32_t udccr; /* 0x000 */
15 uint32_t reserved1;
18 uint32_t udccfr; /* 0x008 */
19 uint32_t reserved2;
22 uint32_t udccs[16]; /* 0x010 - 0x04c */
25 uint32_t uicr0; /* 0x050 */
26 uint32_t uicr1; /* 0x054 */
27 uint32_t usir0; /* 0x058 */
28 uint32_t usir1; /* 0x05c */
31 uint32_t ufnrh; /* 0x060 */
[all …]
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-mx7/
H A Dcrm_regs.h25 uint32_t ccgr;
26 uint32_t ccgr_set;
27 uint32_t ccgr_clr;
28 uint32_t ccgr_tog;
32 uint32_t target_root;
33 uint32_t target_root_set;
34 uint32_t target_root_clr;
35 uint32_t target_root_tog;
36 uint32_t reserved_0[4];
37 uint32_t post;
[all …]

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