1*e1cfe1c9SJoseph Chen /* 2*e1cfe1c9SJoseph Chen * (C) Copyright 2021 Rockchip Electronics Co., Ltd. 3*e1cfe1c9SJoseph Chen * 4*e1cfe1c9SJoseph Chen * SPDX-License-Identifier: GPL-2.0+ 5*e1cfe1c9SJoseph Chen */ 6*e1cfe1c9SJoseph Chen #ifndef _ASM_ARCH_GRF_RK3588_H 7*e1cfe1c9SJoseph Chen #define _ASM_ARCH_GRF_RK3588_H 8*e1cfe1c9SJoseph Chen 9*e1cfe1c9SJoseph Chen #include <common.h> 10*e1cfe1c9SJoseph Chen 11*e1cfe1c9SJoseph Chen struct rk3588_sys_grf { 12*e1cfe1c9SJoseph Chen uint32_t wdt_con0; /* Address Offset: 0x0000 */ 13*e1cfe1c9SJoseph Chen uint32_t reserved0004[3]; /* Address Offset: 0x0004 */ 14*e1cfe1c9SJoseph Chen uint32_t uart_con0; /* Address Offset: 0x0010 */ 15*e1cfe1c9SJoseph Chen uint32_t uart_con1; /* Address Offset: 0x0014 */ 16*e1cfe1c9SJoseph Chen uint32_t reserved0018[42]; /* Address Offset: 0x0018 */ 17*e1cfe1c9SJoseph Chen uint32_t gic_con0; /* Address Offset: 0x00C0 */ 18*e1cfe1c9SJoseph Chen uint32_t reserved00c4[79]; /* Address Offset: 0x00C4 */ 19*e1cfe1c9SJoseph Chen uint32_t memcfg_con0; /* Address Offset: 0x0200 */ 20*e1cfe1c9SJoseph Chen uint32_t memcfg_con1; /* Address Offset: 0x0204 */ 21*e1cfe1c9SJoseph Chen uint32_t memcfg_con2; /* Address Offset: 0x0208 */ 22*e1cfe1c9SJoseph Chen uint32_t memcfg_con3; /* Address Offset: 0x020C */ 23*e1cfe1c9SJoseph Chen uint32_t memcfg_con4; /* Address Offset: 0x0210 */ 24*e1cfe1c9SJoseph Chen uint32_t memcfg_con5; /* Address Offset: 0x0214 */ 25*e1cfe1c9SJoseph Chen uint32_t memcfg_con6; /* Address Offset: 0x0218 */ 26*e1cfe1c9SJoseph Chen uint32_t memcfg_con7; /* Address Offset: 0x021C */ 27*e1cfe1c9SJoseph Chen uint32_t memcfg_con8; /* Address Offset: 0x0220 */ 28*e1cfe1c9SJoseph Chen uint32_t memcfg_con9; /* Address Offset: 0x0224 */ 29*e1cfe1c9SJoseph Chen uint32_t memcfg_con10; /* Address Offset: 0x0228 */ 30*e1cfe1c9SJoseph Chen uint32_t memcfg_con11; /* Address Offset: 0x022C */ 31*e1cfe1c9SJoseph Chen uint32_t memcfg_con12; /* Address Offset: 0x0230 */ 32*e1cfe1c9SJoseph Chen uint32_t memcfg_con13; /* Address Offset: 0x0234 */ 33*e1cfe1c9SJoseph Chen uint32_t memcfg_con14; /* Address Offset: 0x0238 */ 34*e1cfe1c9SJoseph Chen uint32_t memcfg_con15; /* Address Offset: 0x023C */ 35*e1cfe1c9SJoseph Chen uint32_t memcfg_con16; /* Address Offset: 0x0240 */ 36*e1cfe1c9SJoseph Chen uint32_t memcfg_con17; /* Address Offset: 0x0244 */ 37*e1cfe1c9SJoseph Chen uint32_t memcfg_con18; /* Address Offset: 0x0248 */ 38*e1cfe1c9SJoseph Chen uint32_t memcfg_con19; /* Address Offset: 0x024C */ 39*e1cfe1c9SJoseph Chen uint32_t memcfg_con20; /* Address Offset: 0x0250 */ 40*e1cfe1c9SJoseph Chen uint32_t memcfg_con21; /* Address Offset: 0x0254 */ 41*e1cfe1c9SJoseph Chen uint32_t memcfg_con22; /* Address Offset: 0x0258 */ 42*e1cfe1c9SJoseph Chen uint32_t memcfg_con23; /* Address Offset: 0x025C */ 43*e1cfe1c9SJoseph Chen uint32_t memcfg_con24; /* Address Offset: 0x0260 */ 44*e1cfe1c9SJoseph Chen uint32_t reserved0264; /* Address Offset: 0x0264 */ 45*e1cfe1c9SJoseph Chen uint32_t memcfg_con26; /* Address Offset: 0x0268 */ 46*e1cfe1c9SJoseph Chen uint32_t memcfg_con27; /* Address Offset: 0x026C */ 47*e1cfe1c9SJoseph Chen uint32_t memcfg_con28; /* Address Offset: 0x0270 */ 48*e1cfe1c9SJoseph Chen uint32_t memcfg_con29; /* Address Offset: 0x0274 */ 49*e1cfe1c9SJoseph Chen uint32_t memcfg_con30; /* Address Offset: 0x0278 */ 50*e1cfe1c9SJoseph Chen uint32_t memcfg_con31; /* Address Offset: 0x027C */ 51*e1cfe1c9SJoseph Chen uint32_t reserved0280[33]; /* Address Offset: 0x0280 */ 52*e1cfe1c9SJoseph Chen uint32_t soc_con1; /* Address Offset: 0x0304 */ 53*e1cfe1c9SJoseph Chen uint32_t soc_con2; /* Address Offset: 0x0308 */ 54*e1cfe1c9SJoseph Chen uint32_t soc_con3; /* Address Offset: 0x030C */ 55*e1cfe1c9SJoseph Chen uint32_t reserved0310[2]; /* Address Offset: 0x0310 */ 56*e1cfe1c9SJoseph Chen uint32_t soc_con6; /* Address Offset: 0x0318 */ 57*e1cfe1c9SJoseph Chen uint32_t soc_con7; /* Address Offset: 0x031C */ 58*e1cfe1c9SJoseph Chen uint32_t soc_con8; /* Address Offset: 0x0320 */ 59*e1cfe1c9SJoseph Chen uint32_t soc_con9; /* Address Offset: 0x0324 */ 60*e1cfe1c9SJoseph Chen uint32_t soc_con10; /* Address Offset: 0x0328 */ 61*e1cfe1c9SJoseph Chen uint32_t soc_con11; /* Address Offset: 0x032C */ 62*e1cfe1c9SJoseph Chen uint32_t soc_con12; /* Address Offset: 0x0330 */ 63*e1cfe1c9SJoseph Chen uint32_t soc_con13; /* Address Offset: 0x0334 */ 64*e1cfe1c9SJoseph Chen uint32_t reserved0338[18]; /* Address Offset: 0x0338 */ 65*e1cfe1c9SJoseph Chen uint32_t soc_status0; /* Address Offset: 0x0380 */ 66*e1cfe1c9SJoseph Chen uint32_t soc_status1; /* Address Offset: 0x0384 */ 67*e1cfe1c9SJoseph Chen uint32_t soc_status2; /* Address Offset: 0x0388 */ 68*e1cfe1c9SJoseph Chen uint32_t soc_status3; /* Address Offset: 0x038C */ 69*e1cfe1c9SJoseph Chen uint32_t reserved0390[92]; /* Address Offset: 0x0390 */ 70*e1cfe1c9SJoseph Chen uint32_t otp_key08; /* Address Offset: 0x0500 */ 71*e1cfe1c9SJoseph Chen uint32_t otp_key0d; /* Address Offset: 0x0504 */ 72*e1cfe1c9SJoseph Chen uint32_t otp_key0e; /* Address Offset: 0x0508 */ 73*e1cfe1c9SJoseph Chen uint32_t reserved050c[61]; /* Address Offset: 0x050C */ 74*e1cfe1c9SJoseph Chen uint32_t chip_id; /* Address Offset: 0x0600 */ 75*e1cfe1c9SJoseph Chen }; 76*e1cfe1c9SJoseph Chen check_member(rk3588_sys_grf, chip_id, 0x0600); 77*e1cfe1c9SJoseph Chen 78*e1cfe1c9SJoseph Chen struct rk3588_php_grf { 79*e1cfe1c9SJoseph Chen uint32_t php_con0; /* Address Offset: 0x0000 */ 80*e1cfe1c9SJoseph Chen uint32_t php_con1; /* Address Offset: 0x0004 */ 81*e1cfe1c9SJoseph Chen uint32_t gmac_con0; /* Address Offset: 0x0008 */ 82*e1cfe1c9SJoseph Chen uint32_t reserved000c; /* Address Offset: 0x000C */ 83*e1cfe1c9SJoseph Chen uint32_t sata_con0; /* Address Offset: 0x0010 */ 84*e1cfe1c9SJoseph Chen uint32_t sata_con1; /* Address Offset: 0x0014 */ 85*e1cfe1c9SJoseph Chen uint32_t sata_con2; /* Address Offset: 0x0018 */ 86*e1cfe1c9SJoseph Chen uint32_t php_mmu_con0; /* Address Offset: 0x001C */ 87*e1cfe1c9SJoseph Chen uint32_t php_mmu_con1; /* Address Offset: 0x0020 */ 88*e1cfe1c9SJoseph Chen uint32_t php_mmu_con2; /* Address Offset: 0x0024 */ 89*e1cfe1c9SJoseph Chen uint32_t its_taddr0; /* Address Offset: 0x0028 */ 90*e1cfe1c9SJoseph Chen uint32_t its_taddr1; /* Address Offset: 0x002C */ 91*e1cfe1c9SJoseph Chen uint32_t pcie_mmu_pciemode; /* Address Offset: 0x0030 */ 92*e1cfe1c9SJoseph Chen uint32_t pcie_mmu_con0; /* Address Offset: 0x0034 */ 93*e1cfe1c9SJoseph Chen uint32_t pcie_mmu_con1; /* Address Offset: 0x0038 */ 94*e1cfe1c9SJoseph Chen uint32_t pcie_mmu_con2; /* Address Offset: 0x003C */ 95*e1cfe1c9SJoseph Chen uint32_t mem_con0; /* Address Offset: 0x0040 */ 96*e1cfe1c9SJoseph Chen uint32_t php_st0; /* Address Offset: 0x0044 */ 97*e1cfe1c9SJoseph Chen uint32_t php_st1; /* Address Offset: 0x0048 */ 98*e1cfe1c9SJoseph Chen uint32_t php_st2; /* Address Offset: 0x004C */ 99*e1cfe1c9SJoseph Chen uint32_t php_st3; /* Address Offset: 0x0050 */ 100*e1cfe1c9SJoseph Chen uint32_t php_st4; /* Address Offset: 0x0054 */ 101*e1cfe1c9SJoseph Chen uint32_t mmu_pmu_ack; /* Address Offset: 0x0058 */ 102*e1cfe1c9SJoseph Chen uint32_t pcie_mmu_con6; /* Address Offset: 0x005C */ 103*e1cfe1c9SJoseph Chen uint32_t pcie_mmu_con7; /* Address Offset: 0x0060 */ 104*e1cfe1c9SJoseph Chen uint32_t mem_con5; /* Address Offset: 0x0064 */ 105*e1cfe1c9SJoseph Chen uint32_t mem_con10; /* Address Offset: 0x0068 */ 106*e1cfe1c9SJoseph Chen uint32_t reserved006c; /* Address Offset: 0x006C */ 107*e1cfe1c9SJoseph Chen uint32_t clk_con1; /* Address Offset: 0x0070 */ 108*e1cfe1c9SJoseph Chen uint32_t gmac0_sid_aw; /* Address Offset: 0x0074 */ 109*e1cfe1c9SJoseph Chen uint32_t gmac0_ssid_aw; /* Address Offset: 0x0078 */ 110*e1cfe1c9SJoseph Chen uint32_t gmac1_sid_aw; /* Address Offset: 0x007C */ 111*e1cfe1c9SJoseph Chen uint32_t gmac1_ssid_aw; /* Address Offset: 0x0080 */ 112*e1cfe1c9SJoseph Chen uint32_t sata0_sid_aw; /* Address Offset: 0x0084 */ 113*e1cfe1c9SJoseph Chen uint32_t sata0_ssid_aw; /* Address Offset: 0x0088 */ 114*e1cfe1c9SJoseph Chen uint32_t sata1_sid_aw; /* Address Offset: 0x008C */ 115*e1cfe1c9SJoseph Chen uint32_t sata1_ssid_aw; /* Address Offset: 0x0090 */ 116*e1cfe1c9SJoseph Chen uint32_t sata2_sid_aw; /* Address Offset: 0x0094 */ 117*e1cfe1c9SJoseph Chen uint32_t sata2_ssid_aw; /* Address Offset: 0x0098 */ 118*e1cfe1c9SJoseph Chen uint32_t gmac0_sid_ar; /* Address Offset: 0x009C */ 119*e1cfe1c9SJoseph Chen uint32_t gmac0_ssid_ar; /* Address Offset: 0x00A0 */ 120*e1cfe1c9SJoseph Chen uint32_t gmac1_sid_ar; /* Address Offset: 0x00A4 */ 121*e1cfe1c9SJoseph Chen uint32_t gmac1_ssid_ar; /* Address Offset: 0x00A8 */ 122*e1cfe1c9SJoseph Chen uint32_t sata0_sid_ar; /* Address Offset: 0x00AC */ 123*e1cfe1c9SJoseph Chen uint32_t sata0_ssid_ar; /* Address Offset: 0x00B0 */ 124*e1cfe1c9SJoseph Chen uint32_t sata1_sid_ar; /* Address Offset: 0x00B4 */ 125*e1cfe1c9SJoseph Chen uint32_t sata1_ssid_ar; /* Address Offset: 0x00B8 */ 126*e1cfe1c9SJoseph Chen uint32_t sata2_sid_ar; /* Address Offset: 0x00BC */ 127*e1cfe1c9SJoseph Chen uint32_t sata2_ssid_ar; /* Address Offset: 0x00C0 */ 128*e1cfe1c9SJoseph Chen uint32_t usb3otg_2_sid_ar; /* Address Offset: 0x00C4 */ 129*e1cfe1c9SJoseph Chen uint32_t usb3otg_2_ssid_ar; /* Address Offset: 0x00C8 */ 130*e1cfe1c9SJoseph Chen uint32_t usb3otg_2_sid_aw; /* Address Offset: 0x00CC */ 131*e1cfe1c9SJoseph Chen uint32_t usb3otg_2_ssid_aw; /* Address Offset: 0x00D0 */ 132*e1cfe1c9SJoseph Chen uint32_t gmac_con_pst; /* Address Offset: 0x00D4 */ 133*e1cfe1c9SJoseph Chen uint32_t gmac0_cmd; /* Address Offset: 0x00D8 */ 134*e1cfe1c9SJoseph Chen uint32_t gmac1_cmd; /* Address Offset: 0x00DC */ 135*e1cfe1c9SJoseph Chen uint32_t mem_con11; /* Address Offset: 0x00E0 */ 136*e1cfe1c9SJoseph Chen uint32_t usb3otg_2_con0; /* Address Offset: 0x00E4 */ 137*e1cfe1c9SJoseph Chen uint32_t usb3otg_2_con1; /* Address Offset: 0x00E8 */ 138*e1cfe1c9SJoseph Chen uint32_t usb3otg_2_intcon; /* Address Offset: 0x00EC */ 139*e1cfe1c9SJoseph Chen uint32_t usb3otg_2_st_lat0; /* Address Offset: 0x00F0 */ 140*e1cfe1c9SJoseph Chen uint32_t usb3otg_2_st_lat1; /* Address Offset: 0x00F4 */ 141*e1cfe1c9SJoseph Chen uint32_t usb3otg_2_st_cb; /* Address Offset: 0x00F8 */ 142*e1cfe1c9SJoseph Chen uint32_t usb3otg_2_st; /* Address Offset: 0x00FC */ 143*e1cfe1c9SJoseph Chen uint32_t pciesel_con; /* Address Offset: 0x0100 */ 144*e1cfe1c9SJoseph Chen uint32_t utmi_con; /* Address Offset: 0x0104 */ 145*e1cfe1c9SJoseph Chen uint32_t reserved0108; /* Address Offset: 0x0108 */ 146*e1cfe1c9SJoseph Chen uint32_t pcie4l_sid_aw; /* Address Offset: 0x010C */ 147*e1cfe1c9SJoseph Chen uint32_t pcie4l_sid_ar; /* Address Offset: 0x0110 */ 148*e1cfe1c9SJoseph Chen uint32_t pcie2l_sid_aw; /* Address Offset: 0x0114 */ 149*e1cfe1c9SJoseph Chen uint32_t pcie2l_sid_ar; /* Address Offset: 0x0118 */ 150*e1cfe1c9SJoseph Chen uint32_t pcie1l0_sid_aw; /* Address Offset: 0x011C */ 151*e1cfe1c9SJoseph Chen uint32_t pcie1l0_sid_ar; /* Address Offset: 0x0120 */ 152*e1cfe1c9SJoseph Chen uint32_t pcie1l1_sid_aw; /* Address Offset: 0x0124 */ 153*e1cfe1c9SJoseph Chen uint32_t pcie1l1_sid_ar; /* Address Offset: 0x0128 */ 154*e1cfe1c9SJoseph Chen uint32_t pcie1l2_sid_aw; /* Address Offset: 0x012C */ 155*e1cfe1c9SJoseph Chen uint32_t pcie1l2_sid_ar; /* Address Offset: 0x0130 */ 156*e1cfe1c9SJoseph Chen uint32_t reserved0134; /* Address Offset: 0x0134 */ 157*e1cfe1c9SJoseph Chen uint32_t pcie_ats; /* Address Offset: 0x0138 */ 158*e1cfe1c9SJoseph Chen uint32_t st_utmi; /* Address Offset: 0x013C */ 159*e1cfe1c9SJoseph Chen uint32_t reserved0140; /* Address Offset: 0x0140 */ 160*e1cfe1c9SJoseph Chen uint32_t pcie4l_ssid_aw; /* Address Offset: 0x0144 */ 161*e1cfe1c9SJoseph Chen uint32_t pcie4l_ssid_ar; /* Address Offset: 0x0148 */ 162*e1cfe1c9SJoseph Chen uint32_t pcie2l_ssid_aw; /* Address Offset: 0x014C */ 163*e1cfe1c9SJoseph Chen uint32_t pcie2l_ssid_ar; /* Address Offset: 0x0150 */ 164*e1cfe1c9SJoseph Chen uint32_t pcie1l0_ssid_aw; /* Address Offset: 0x0154 */ 165*e1cfe1c9SJoseph Chen uint32_t pcie1l0_ssid_ar; /* Address Offset: 0x0158 */ 166*e1cfe1c9SJoseph Chen uint32_t pcie1l1_ssid_aw; /* Address Offset: 0x015C */ 167*e1cfe1c9SJoseph Chen uint32_t pcie1l1_ssid_ar; /* Address Offset: 0x0160 */ 168*e1cfe1c9SJoseph Chen uint32_t pcie1l2_ssid_aw; /* Address Offset: 0x0164 */ 169*e1cfe1c9SJoseph Chen uint32_t pcie1l2_ssid_ar; /* Address Offset: 0x0168 */ 170*e1cfe1c9SJoseph Chen uint32_t pcie_ssid_v; /* Address Offset: 0x016C */ 171*e1cfe1c9SJoseph Chen uint32_t reserved0170; /* Address Offset: 0x0170 */ 172*e1cfe1c9SJoseph Chen uint32_t sata_pd_sel; /* Address Offset: 0x0174 */ 173*e1cfe1c9SJoseph Chen uint32_t pcie_mmu_irq_clr; /* Address Offset: 0x0178 */ 174*e1cfe1c9SJoseph Chen uint32_t php_mmu_irq_clr; /* Address Offset: 0x017C */ 175*e1cfe1c9SJoseph Chen uint32_t pcie_mmu_st; /* Address Offset: 0x0180 */ 176*e1cfe1c9SJoseph Chen uint32_t php_mmu_st; /* Address Offset: 0x0184 */ 177*e1cfe1c9SJoseph Chen uint32_t reserved0188; /* Address Offset: 0x0188 */ 178*e1cfe1c9SJoseph Chen uint32_t php_st0b; /* Address Offset: 0x018C */ 179*e1cfe1c9SJoseph Chen }; 180*e1cfe1c9SJoseph Chen check_member(rk3588_php_grf, php_st0b, 0x018c); 181*e1cfe1c9SJoseph Chen 182*e1cfe1c9SJoseph Chen #endif 183