1bf72c9c9SXuhui Lin /* 2bf72c9c9SXuhui Lin * (C) Copyright 2021 Rockchip Electronics Co., Ltd. 3bf72c9c9SXuhui Lin * 4bf72c9c9SXuhui Lin * SPDX-License-Identifier: GPL-2.0+ 5bf72c9c9SXuhui Lin */ 6bf72c9c9SXuhui Lin #ifndef _ASM_ARCH_GRF_RK3576_H 7bf72c9c9SXuhui Lin #define _ASM_ARCH_GRF_RK3576_H 8bf72c9c9SXuhui Lin 9bf72c9c9SXuhui Lin #include <common.h> 10bf72c9c9SXuhui Lin 11bf72c9c9SXuhui Lin /* bigcore_grf register structure define */ 12bf72c9c9SXuhui Lin struct rk3576_bigcore_grf_reg { 13bf72c9c9SXuhui Lin uint32_t reserved0000[11]; /* address offset: 0x0000 */ 14bf72c9c9SXuhui Lin uint32_t cpu_status[1]; /* address offset: 0x002c */ 15bf72c9c9SXuhui Lin uint32_t reserved0030; /* address offset: 0x0030 */ 16bf72c9c9SXuhui Lin uint32_t cpu_con[2]; /* address offset: 0x0034 */ 17bf72c9c9SXuhui Lin uint32_t cpu_mem_cfg_hdsprf; /* address offset: 0x003c */ 18bf72c9c9SXuhui Lin uint32_t reserved0040; /* address offset: 0x0040 */ 19bf72c9c9SXuhui Lin uint32_t cpu_mem_cfg_hssprf; /* address offset: 0x0044 */ 20bf72c9c9SXuhui Lin }; 21bf72c9c9SXuhui Lin 22bf72c9c9SXuhui Lin check_member(rk3576_bigcore_grf_reg, cpu_mem_cfg_hssprf, 0x0044); 23bf72c9c9SXuhui Lin 24bf72c9c9SXuhui Lin /* cci_grf register structure define */ 25bf72c9c9SXuhui Lin struct rk3576_cci_grf_reg { 26bf72c9c9SXuhui Lin uint32_t cci_con[5]; /* address offset: 0x0000 */ 27bf72c9c9SXuhui Lin uint32_t reserved0014[8]; /* address offset: 0x0014 */ 28bf72c9c9SXuhui Lin uint32_t cci_status[5]; /* address offset: 0x0034 */ 29bf72c9c9SXuhui Lin uint32_t reserved0048[3]; /* address offset: 0x0048 */ 30bf72c9c9SXuhui Lin uint32_t cci_mem_cfg_hdsprf; /* address offset: 0x0054 */ 31bf72c9c9SXuhui Lin }; 32bf72c9c9SXuhui Lin 33bf72c9c9SXuhui Lin check_member(rk3576_cci_grf_reg, cci_mem_cfg_hdsprf, 0x0054); 34bf72c9c9SXuhui Lin 35bf72c9c9SXuhui Lin /* center_grf register structure define */ 36bf72c9c9SXuhui Lin struct rk3576_center_grf_reg { 37bf72c9c9SXuhui Lin uint32_t soc_con[6]; /* address offset: 0x0000 */ 38bf72c9c9SXuhui Lin }; 39bf72c9c9SXuhui Lin 40bf72c9c9SXuhui Lin check_member(rk3576_center_grf_reg, soc_con, 0x0000); 41bf72c9c9SXuhui Lin 42bf72c9c9SXuhui Lin /* combo_pipe_phy_grf register structure define */ 43bf72c9c9SXuhui Lin struct rk3576_combo_pipe_phy_grf_reg { 44bf72c9c9SXuhui Lin uint32_t pipe_con[5]; /* address offset: 0x0000 */ 45bf72c9c9SXuhui Lin uint32_t reserved0014[8]; /* address offset: 0x0014 */ 46bf72c9c9SXuhui Lin uint32_t pipe_status[1]; /* address offset: 0x0034 */ 47bf72c9c9SXuhui Lin uint32_t reserved0038[18]; /* address offset: 0x0038 */ 48bf72c9c9SXuhui Lin uint32_t lfps_det_con; /* address offset: 0x0080 */ 49bf72c9c9SXuhui Lin uint32_t reserved0084[7]; /* address offset: 0x0084 */ 50bf72c9c9SXuhui Lin uint32_t phy_int_en; /* address offset: 0x00a0 */ 51bf72c9c9SXuhui Lin uint32_t phy_int_status; /* address offset: 0x00a4 */ 52bf72c9c9SXuhui Lin }; 53bf72c9c9SXuhui Lin 54bf72c9c9SXuhui Lin check_member(rk3576_combo_pipe_phy_grf_reg, phy_int_status, 0x00a4); 55bf72c9c9SXuhui Lin 56bf72c9c9SXuhui Lin /* csidphy_grf register structure define */ 57bf72c9c9SXuhui Lin struct rk3576_csidphy_grf_reg { 58bf72c9c9SXuhui Lin uint32_t con[1]; /* address offset: 0x0000 */ 59bf72c9c9SXuhui Lin uint32_t reserved0004[31]; /* address offset: 0x0004 */ 60bf72c9c9SXuhui Lin uint32_t status[1]; /* address offset: 0x0080 */ 61bf72c9c9SXuhui Lin }; 62bf72c9c9SXuhui Lin 63bf72c9c9SXuhui Lin check_member(rk3576_csidphy_grf_reg, status, 0x0080); 64bf72c9c9SXuhui Lin 65bf72c9c9SXuhui Lin /* dcphy_grf register structure define */ 66bf72c9c9SXuhui Lin struct rk3576_dcphy_grf_reg { 67bf72c9c9SXuhui Lin uint32_t con[2]; /* address offset: 0x0000 */ 68bf72c9c9SXuhui Lin uint32_t reserved0008[30]; /* address offset: 0x0008 */ 69bf72c9c9SXuhui Lin uint32_t status[3]; /* address offset: 0x0080 */ 70bf72c9c9SXuhui Lin }; 71bf72c9c9SXuhui Lin 72bf72c9c9SXuhui Lin check_member(rk3576_dcphy_grf_reg, status, 0x0080); 73bf72c9c9SXuhui Lin 74bf72c9c9SXuhui Lin /* ddr_grf register structure define */ 75bf72c9c9SXuhui Lin struct rk3576_ddr_grf_reg { 76bf72c9c9SXuhui Lin uint32_t cha_con[20]; /* address offset: 0x0000 */ 77bf72c9c9SXuhui Lin uint32_t reserved0050[44]; /* address offset: 0x0050 */ 78bf72c9c9SXuhui Lin uint32_t chb_con[20]; /* address offset: 0x0100 */ 79bf72c9c9SXuhui Lin uint32_t reserved0150[44]; /* address offset: 0x0150 */ 80bf72c9c9SXuhui Lin uint32_t cha_status[12]; /* address offset: 0x0200 */ 81bf72c9c9SXuhui Lin uint32_t reserved0230[52]; /* address offset: 0x0230 */ 82bf72c9c9SXuhui Lin uint32_t chb_status[12]; /* address offset: 0x0300 */ 83bf72c9c9SXuhui Lin uint32_t reserved0330[128]; /* address offset: 0x0330 */ 84bf72c9c9SXuhui Lin uint32_t cha_phy_con[1]; /* address offset: 0x0530 */ 85bf72c9c9SXuhui Lin uint32_t chb_phy_con[1]; /* address offset: 0x0534 */ 86bf72c9c9SXuhui Lin uint32_t cha_phy_status[1]; /* address offset: 0x0538 */ 87bf72c9c9SXuhui Lin uint32_t chb_phy_status[1]; /* address offset: 0x053c */ 88bf72c9c9SXuhui Lin uint32_t common_con[6]; /* address offset: 0x0540 */ 89bf72c9c9SXuhui Lin uint32_t reserved0558[10]; /* address offset: 0x0558 */ 90bf72c9c9SXuhui Lin uint32_t status[1]; /* address offset: 0x0580 */ 91bf72c9c9SXuhui Lin }; 92bf72c9c9SXuhui Lin 93bf72c9c9SXuhui Lin check_member(rk3576_ddr_grf_reg, status, 0x0580); 94bf72c9c9SXuhui Lin 95bf72c9c9SXuhui Lin /* gpu_grf register structure define */ 96bf72c9c9SXuhui Lin struct rk3576_gpu_grf_reg { 97bf72c9c9SXuhui Lin uint32_t reserved0000[8]; /* address offset: 0x0000 */ 98bf72c9c9SXuhui Lin uint32_t gpu_con[1]; /* address offset: 0x0020 */ 99bf72c9c9SXuhui Lin uint32_t reserved0024[6]; /* address offset: 0x0024 */ 100bf72c9c9SXuhui Lin uint32_t gpu_mem_cfg_hdsprf; /* address offset: 0x003c */ 101bf72c9c9SXuhui Lin uint32_t gpu_mem_cfg_hsspra; /* address offset: 0x0040 */ 102bf72c9c9SXuhui Lin uint32_t reserved0044; /* address offset: 0x0044 */ 103bf72c9c9SXuhui Lin uint32_t gpu_mem_cfg_uhdpdprf_low; /* address offset: 0x0048 */ 104bf72c9c9SXuhui Lin }; 105bf72c9c9SXuhui Lin 106bf72c9c9SXuhui Lin check_member(rk3576_gpu_grf_reg, gpu_mem_cfg_uhdpdprf_low, 0x0048); 107bf72c9c9SXuhui Lin 108bf72c9c9SXuhui Lin /* usb2phy_grf register structure define */ 109bf72c9c9SXuhui Lin struct rk3576_usb2phy_grf_reg { 110bf72c9c9SXuhui Lin uint32_t con[6]; /* address offset: 0x0000 */ 111bf72c9c9SXuhui Lin uint32_t reserved0018[2]; /* address offset: 0x0018 */ 112bf72c9c9SXuhui Lin uint32_t ls_con; /* address offset: 0x0020 */ 113bf72c9c9SXuhui Lin uint32_t dis_con; /* address offset: 0x0024 */ 114bf72c9c9SXuhui Lin uint32_t bvalid_con; /* address offset: 0x0028 */ 115bf72c9c9SXuhui Lin uint32_t id_con; /* address offset: 0x002c */ 116bf72c9c9SXuhui Lin uint32_t vbusvalid_con; /* address offset: 0x0030 */ 117bf72c9c9SXuhui Lin uint32_t reserved0034[3]; /* address offset: 0x0034 */ 118bf72c9c9SXuhui Lin uint32_t dbg_con[1]; /* address offset: 0x0040 */ 119bf72c9c9SXuhui Lin uint32_t linest_timeout; /* address offset: 0x0044 */ 120bf72c9c9SXuhui Lin uint32_t linest_deb; /* address offset: 0x0048 */ 121bf72c9c9SXuhui Lin uint32_t rx_timeout; /* address offset: 0x004c */ 122bf72c9c9SXuhui Lin uint32_t seq_limt; /* address offset: 0x0050 */ 123bf72c9c9SXuhui Lin uint32_t linest_cnt_st; /* address offset: 0x0054 */ 124bf72c9c9SXuhui Lin uint32_t dbg_st; /* address offset: 0x0058 */ 125bf72c9c9SXuhui Lin uint32_t rx_cnt_st; /* address offset: 0x005c */ 126bf72c9c9SXuhui Lin uint32_t reserved0060[8]; /* address offset: 0x0060 */ 127bf72c9c9SXuhui Lin uint32_t st[1]; /* address offset: 0x0080 */ 128bf72c9c9SXuhui Lin uint32_t reserved0084[15]; /* address offset: 0x0084 */ 129bf72c9c9SXuhui Lin uint32_t int_en; /* address offset: 0x00c0 */ 130bf72c9c9SXuhui Lin uint32_t int_st; /* address offset: 0x00c4 */ 131bf72c9c9SXuhui Lin uint32_t int_st_clr; /* address offset: 0x00c8 */ 132bf72c9c9SXuhui Lin uint32_t reserved00cc; /* address offset: 0x00cc */ 133bf72c9c9SXuhui Lin uint32_t detclk_sel; /* address offset: 0x00d0 */ 134bf72c9c9SXuhui Lin }; 135bf72c9c9SXuhui Lin 136bf72c9c9SXuhui Lin check_member(rk3576_usb2phy_grf_reg, detclk_sel, 0x00d0); 137bf72c9c9SXuhui Lin 138bf72c9c9SXuhui Lin /* hdptxphy_grf register structure define */ 139bf72c9c9SXuhui Lin struct rk3576_hdptxphy_grf_reg { 140bf72c9c9SXuhui Lin uint32_t con[2]; /* address offset: 0x0000 */ 141bf72c9c9SXuhui Lin uint32_t reserved0008[30]; /* address offset: 0x0008 */ 142bf72c9c9SXuhui Lin uint32_t status[1]; /* address offset: 0x0080 */ 143bf72c9c9SXuhui Lin }; 144bf72c9c9SXuhui Lin 145bf72c9c9SXuhui Lin check_member(rk3576_hdptxphy_grf_reg, status, 0x0080); 146bf72c9c9SXuhui Lin 147bf72c9c9SXuhui Lin /* litcore_grf register structure define */ 148bf72c9c9SXuhui Lin struct rk3576_litcore_grf_reg { 149bf72c9c9SXuhui Lin uint32_t reserved0000[11]; /* address offset: 0x0000 */ 150bf72c9c9SXuhui Lin uint32_t cpu_status[1]; /* address offset: 0x002c */ 151bf72c9c9SXuhui Lin uint32_t reserved0030; /* address offset: 0x0030 */ 152bf72c9c9SXuhui Lin uint32_t cpu_con[2]; /* address offset: 0x0034 */ 153bf72c9c9SXuhui Lin uint32_t cpu_mem_cfg_hdsprf; /* address offset: 0x003c */ 154bf72c9c9SXuhui Lin uint32_t reserved0040; /* address offset: 0x0040 */ 155bf72c9c9SXuhui Lin uint32_t cpu_mem_cfg_hssprf; /* address offset: 0x0044 */ 156bf72c9c9SXuhui Lin }; 157bf72c9c9SXuhui Lin 158bf72c9c9SXuhui Lin check_member(rk3576_litcore_grf_reg, cpu_mem_cfg_hssprf, 0x0044); 159bf72c9c9SXuhui Lin 160bf72c9c9SXuhui Lin /* mphy_grf register structure define */ 161bf72c9c9SXuhui Lin struct rk3576_mphy_grf_reg { 162bf72c9c9SXuhui Lin uint32_t con[2]; /* address offset: 0x0000 */ 163bf72c9c9SXuhui Lin uint32_t status[1]; /* address offset: 0x0008 */ 164bf72c9c9SXuhui Lin }; 165bf72c9c9SXuhui Lin 166bf72c9c9SXuhui Lin check_member(rk3576_mphy_grf_reg, status, 0x0008); 167bf72c9c9SXuhui Lin 168bf72c9c9SXuhui Lin /* npu_grf register structure define */ 169bf72c9c9SXuhui Lin struct rk3576_npu_grf_reg { 170bf72c9c9SXuhui Lin uint32_t reserved0000[2]; /* address offset: 0x0000 */ 171bf72c9c9SXuhui Lin uint32_t mem_con[3]; /* address offset: 0x0008 */ 172bf72c9c9SXuhui Lin uint32_t memgate_con[2]; /* address offset: 0x0014 */ 173bf72c9c9SXuhui Lin uint32_t rknnst; /* address offset: 0x001c */ 174bf72c9c9SXuhui Lin uint32_t nsp_slv_addr; /* address offset: 0x0020 */ 175bf72c9c9SXuhui Lin uint32_t reserved0024; /* address offset: 0x0024 */ 176bf72c9c9SXuhui Lin uint32_t nputop_con; /* address offset: 0x0028 */ 177bf72c9c9SXuhui Lin uint32_t stcalib; /* address offset: 0x002c */ 178bf72c9c9SXuhui Lin uint32_t start_addr; /* address offset: 0x0030 */ 179bf72c9c9SXuhui Lin uint32_t end_addr; /* address offset: 0x0034 */ 180bf72c9c9SXuhui Lin uint32_t nputop_st; /* address offset: 0x0038 */ 181bf72c9c9SXuhui Lin uint32_t reserved003c[7]; /* address offset: 0x003c */ 182bf72c9c9SXuhui Lin uint32_t cache_maintain; /* address offset: 0x0058 */ 183bf72c9c9SXuhui Lin uint32_t rv_base_addr; /* address offset: 0x005c */ 184bf72c9c9SXuhui Lin uint32_t reserved0060[3]; /* address offset: 0x0060 */ 185bf72c9c9SXuhui Lin uint32_t urgent_con[4]; /* address offset: 0x006c */ 186bf72c9c9SXuhui Lin }; 187bf72c9c9SXuhui Lin 188bf72c9c9SXuhui Lin check_member(rk3576_npu_grf_reg, urgent_con, 0x006c); 189bf72c9c9SXuhui Lin 190bf72c9c9SXuhui Lin /* php_grf register structure define */ 191bf72c9c9SXuhui Lin struct rk3576_php_grf_reg { 192bf72c9c9SXuhui Lin uint32_t mmubp_st; /* address offset: 0x0000 */ 193bf72c9c9SXuhui Lin uint32_t mmubp_con[1]; /* address offset: 0x0004 */ 194bf72c9c9SXuhui Lin uint32_t mmu0_con; /* address offset: 0x0008 */ 195bf72c9c9SXuhui Lin uint32_t mmu1_con; /* address offset: 0x000c */ 196bf72c9c9SXuhui Lin uint32_t mem_con[3]; /* address offset: 0x0010 */ 197bf72c9c9SXuhui Lin uint32_t sata0_con; /* address offset: 0x001c */ 198bf72c9c9SXuhui Lin uint32_t sata1_con; /* address offset: 0x0020 */ 199bf72c9c9SXuhui Lin uint32_t usb3otg1_status_lat[2]; /* address offset: 0x0024 */ 200bf72c9c9SXuhui Lin uint32_t usb3otg1_status_cb; /* address offset: 0x002c */ 201bf72c9c9SXuhui Lin uint32_t usb3otg1_status; /* address offset: 0x0030 */ 202bf72c9c9SXuhui Lin uint32_t usb3otg1_con[2]; /* address offset: 0x0034 */ 203bf72c9c9SXuhui Lin uint32_t reserved003c[3]; /* address offset: 0x003c */ 204bf72c9c9SXuhui Lin uint32_t pciepipe_con[1]; /* address offset: 0x0048 */ 205bf72c9c9SXuhui Lin uint32_t reserved004c[2]; /* address offset: 0x004c */ 206bf72c9c9SXuhui Lin uint32_t pcie_clkreq_st; /* address offset: 0x0054 */ 207bf72c9c9SXuhui Lin uint32_t reserved0058; /* address offset: 0x0058 */ 208bf72c9c9SXuhui Lin uint32_t mmu0_st[5]; /* address offset: 0x005c */ 209bf72c9c9SXuhui Lin uint32_t mmu1_st[5]; /* address offset: 0x0070 */ 210bf72c9c9SXuhui Lin }; 211bf72c9c9SXuhui Lin 212bf72c9c9SXuhui Lin check_member(rk3576_php_grf_reg, mmu1_st, 0x0070); 213bf72c9c9SXuhui Lin 214bf72c9c9SXuhui Lin /* pmu0_grf register structure define */ 215bf72c9c9SXuhui Lin struct rk3576_pmu0_grf_reg { 216bf72c9c9SXuhui Lin uint32_t soc_con[7]; /* address offset: 0x0000 */ 217bf72c9c9SXuhui Lin uint32_t reserved001c; /* address offset: 0x001c */ 218bf72c9c9SXuhui Lin uint32_t io_ret_con[2]; /* address offset: 0x0020 */ 219bf72c9c9SXuhui Lin uint32_t reserved0028[2]; /* address offset: 0x0028 */ 220bf72c9c9SXuhui Lin uint32_t mem_con; /* address offset: 0x0030 */ 221bf72c9c9SXuhui Lin uint32_t reserved0034[3]; /* address offset: 0x0034 */ 222bf72c9c9SXuhui Lin uint32_t os_reg[8]; /* address offset: 0x0040 */ 223bf72c9c9SXuhui Lin }; 224bf72c9c9SXuhui Lin 225bf72c9c9SXuhui Lin check_member(rk3576_pmu0_grf_reg, os_reg, 0x0040); 226bf72c9c9SXuhui Lin 227bf72c9c9SXuhui Lin /* pmu0_sgrf register structure define */ 228bf72c9c9SXuhui Lin struct rk3576_pmu0_sgrf_reg { 229bf72c9c9SXuhui Lin uint32_t soc_con[3]; /* address offset: 0x0000 */ 230bf72c9c9SXuhui Lin uint32_t reserved000c[13]; /* address offset: 0x000c */ 231bf72c9c9SXuhui Lin uint32_t dcie_con[8]; /* address offset: 0x0040 */ 232bf72c9c9SXuhui Lin uint32_t dcie_wlock; /* address offset: 0x0060 */ 233bf72c9c9SXuhui Lin }; 234bf72c9c9SXuhui Lin 235bf72c9c9SXuhui Lin check_member(rk3576_pmu0_sgrf_reg, dcie_wlock, 0x0060); 236bf72c9c9SXuhui Lin 237bf72c9c9SXuhui Lin /* pmu1_grf register structure define */ 238bf72c9c9SXuhui Lin struct rk3576_pmu1_grf_reg { 239bf72c9c9SXuhui Lin uint32_t soc_con[8]; /* address offset: 0x0000 */ 240bf72c9c9SXuhui Lin uint32_t reserved0020[12]; /* address offset: 0x0020 */ 241bf72c9c9SXuhui Lin uint32_t biu_con; /* address offset: 0x0050 */ 242bf72c9c9SXuhui Lin uint32_t biu_status; /* address offset: 0x0054 */ 243bf72c9c9SXuhui Lin uint32_t reserved0058[2]; /* address offset: 0x0058 */ 244bf72c9c9SXuhui Lin uint32_t soc_status; /* address offset: 0x0060 */ 245bf72c9c9SXuhui Lin uint32_t reserved0064[7]; /* address offset: 0x0064 */ 246bf72c9c9SXuhui Lin uint32_t mem_con[2]; /* address offset: 0x0080 */ 247bf72c9c9SXuhui Lin uint32_t reserved0088[30]; /* address offset: 0x0088 */ 248bf72c9c9SXuhui Lin uint32_t func_rst_status; /* address offset: 0x0100 */ 249*4ca69a29SDavid Wu uint32_t func_rst_clr; /* address offset: 0x0104 */ 250bf72c9c9SXuhui Lin uint32_t reserved0108[2]; /* address offset: 0x0108 */ 251bf72c9c9SXuhui Lin uint32_t sd_detect_con; /* address offset: 0x0110 */ 252bf72c9c9SXuhui Lin uint32_t sd_detect_sts; /* address offset: 0x0114 */ 253*4ca69a29SDavid Wu uint32_t sd_detect_clr; /* address offset: 0x0118 */ 254bf72c9c9SXuhui Lin uint32_t sd_detect_cnt; /* address offset: 0x011c */ 255bf72c9c9SXuhui Lin uint32_t reserved0120[56]; /* address offset: 0x0120 */ 256bf72c9c9SXuhui Lin uint32_t os_reg[16]; /* address offset: 0x0200 */ 257bf72c9c9SXuhui Lin }; 258bf72c9c9SXuhui Lin 259bf72c9c9SXuhui Lin check_member(rk3576_pmu1_grf_reg, os_reg, 0x0200); 260bf72c9c9SXuhui Lin 261bf72c9c9SXuhui Lin /* pmu1_sgrf register structure define */ 262bf72c9c9SXuhui Lin struct rk3576_pmu1_sgrf_reg { 263bf72c9c9SXuhui Lin uint32_t soc_con[18]; /* address offset: 0x0000 */ 264bf72c9c9SXuhui Lin }; 265bf72c9c9SXuhui Lin 266bf72c9c9SXuhui Lin check_member(rk3576_pmu1_sgrf_reg, soc_con, 0x0000); 267bf72c9c9SXuhui Lin 268bf72c9c9SXuhui Lin /* sdgmac_grf register structure define */ 269bf72c9c9SXuhui Lin struct rk3576_sdgmac_grf_reg { 270bf72c9c9SXuhui Lin uint32_t mem_con[5]; /* address offset: 0x0000 */ 271bf72c9c9SXuhui Lin uint32_t reserved0014[2]; /* address offset: 0x0014 */ 272bf72c9c9SXuhui Lin uint32_t gmac_st[1]; /* address offset: 0x001c */ 273bf72c9c9SXuhui Lin uint32_t gmac0_con; /* address offset: 0x0020 */ 274bf72c9c9SXuhui Lin uint32_t gmac1_con; /* address offset: 0x0024 */ 275bf72c9c9SXuhui Lin uint32_t gmac0_tp[2]; /* address offset: 0x0028 */ 276bf72c9c9SXuhui Lin uint32_t gmac1_tp[2]; /* address offset: 0x0030 */ 277bf72c9c9SXuhui Lin uint32_t gmac0_cmd; /* address offset: 0x0038 */ 278bf72c9c9SXuhui Lin uint32_t gmac1_cmd; /* address offset: 0x003c */ 279bf72c9c9SXuhui Lin uint32_t reserved0040[2]; /* address offset: 0x0040 */ 280bf72c9c9SXuhui Lin uint32_t mem_gate_con; /* address offset: 0x0048 */ 281bf72c9c9SXuhui Lin }; 282bf72c9c9SXuhui Lin 283bf72c9c9SXuhui Lin check_member(rk3576_sdgmac_grf_reg, mem_gate_con, 0x0048); 284bf72c9c9SXuhui Lin 285bf72c9c9SXuhui Lin /* sys_grf register structure define */ 286bf72c9c9SXuhui Lin struct rk3576_sys_grf_reg { 287bf72c9c9SXuhui Lin uint32_t soc_con[13]; /* address offset: 0x0000 */ 288bf72c9c9SXuhui Lin uint32_t reserved0034[3]; /* address offset: 0x0034 */ 289bf72c9c9SXuhui Lin uint32_t biu_con[6]; /* address offset: 0x0040 */ 290bf72c9c9SXuhui Lin uint32_t reserved0058[2]; /* address offset: 0x0058 */ 291bf72c9c9SXuhui Lin uint32_t biu_status[8]; /* address offset: 0x0060 */ 292bf72c9c9SXuhui Lin uint32_t mem_con[19]; /* address offset: 0x0080 */ 293bf72c9c9SXuhui Lin uint32_t reserved00cc[29]; /* address offset: 0x00cc */ 294bf72c9c9SXuhui Lin uint32_t soc_status[2]; /* address offset: 0x0140 */ 295bf72c9c9SXuhui Lin uint32_t memfault_status[2]; /* address offset: 0x0148 */ 296bf72c9c9SXuhui Lin uint32_t reserved0150[12]; /* address offset: 0x0150 */ 297bf72c9c9SXuhui Lin uint32_t soc_code; /* address offset: 0x0180 */ 298bf72c9c9SXuhui Lin uint32_t reserved0184[3]; /* address offset: 0x0184 */ 299bf72c9c9SXuhui Lin uint32_t soc_version; /* address offset: 0x0190 */ 300bf72c9c9SXuhui Lin uint32_t reserved0194[3]; /* address offset: 0x0194 */ 301bf72c9c9SXuhui Lin uint32_t chip_id; /* address offset: 0x01a0 */ 302bf72c9c9SXuhui Lin uint32_t reserved01a4[3]; /* address offset: 0x01a4 */ 303bf72c9c9SXuhui Lin uint32_t chip_version; /* address offset: 0x01b0 */ 304bf72c9c9SXuhui Lin }; 305bf72c9c9SXuhui Lin 306bf72c9c9SXuhui Lin check_member(rk3576_sys_grf_reg, chip_version, 0x01b0); 307bf72c9c9SXuhui Lin 308bf72c9c9SXuhui Lin /* sys_sgrf register structure define */ 309bf72c9c9SXuhui Lin struct rk3576_sys_sgrf_reg { 310bf72c9c9SXuhui Lin uint32_t ddr_bank_hash_ctrl; /* address offset: 0x0000 */ 311bf72c9c9SXuhui Lin uint32_t ddr_bank_mask[4]; /* address offset: 0x0004 */ 312bf72c9c9SXuhui Lin uint32_t ddr_rank_mask[1]; /* address offset: 0x0014 */ 313bf72c9c9SXuhui Lin uint32_t reserved0018[2]; /* address offset: 0x0018 */ 314bf72c9c9SXuhui Lin uint32_t soc_con[21]; /* address offset: 0x0020 */ 315bf72c9c9SXuhui Lin uint32_t reserved0074[3]; /* address offset: 0x0074 */ 316bf72c9c9SXuhui Lin uint32_t dmac0_con[10]; /* address offset: 0x0080 */ 317bf72c9c9SXuhui Lin uint32_t reserved00a8[22]; /* address offset: 0x00a8 */ 318bf72c9c9SXuhui Lin uint32_t dmac1_con[10]; /* address offset: 0x0100 */ 319bf72c9c9SXuhui Lin uint32_t reserved0128[22]; /* address offset: 0x0128 */ 320bf72c9c9SXuhui Lin uint32_t dmac2_con[10]; /* address offset: 0x0180 */ 321bf72c9c9SXuhui Lin uint32_t reserved01a8[22]; /* address offset: 0x01a8 */ 322bf72c9c9SXuhui Lin uint32_t key_con[2]; /* address offset: 0x0200 */ 323bf72c9c9SXuhui Lin uint32_t key_wlock; /* address offset: 0x0208 */ 324bf72c9c9SXuhui Lin uint32_t reserved020c[13]; /* address offset: 0x020c */ 325bf72c9c9SXuhui Lin uint32_t soc_status; /* address offset: 0x0240 */ 326bf72c9c9SXuhui Lin uint32_t reserved0244[47]; /* address offset: 0x0244 */ 327bf72c9c9SXuhui Lin uint32_t ip_info_con; /* address offset: 0x0300 */ 328bf72c9c9SXuhui Lin }; 329bf72c9c9SXuhui Lin 330bf72c9c9SXuhui Lin check_member(rk3576_sys_sgrf_reg, ip_info_con, 0x0300); 331bf72c9c9SXuhui Lin 332bf72c9c9SXuhui Lin /* ufs_grf register structure define */ 333bf72c9c9SXuhui Lin struct rk3576_ufs_grf_reg { 334bf72c9c9SXuhui Lin uint32_t clk_ctrl; /* address offset: 0x0000 */ 335bf72c9c9SXuhui Lin uint32_t uic_src_sel; /* address offset: 0x0004 */ 336bf72c9c9SXuhui Lin uint32_t ufs_state_ie; /* address offset: 0x0008 */ 337bf72c9c9SXuhui Lin uint32_t ufs_state_is; /* address offset: 0x000c */ 338bf72c9c9SXuhui Lin uint32_t ufs_state; /* address offset: 0x0010 */ 339bf72c9c9SXuhui Lin uint32_t reserved0014[13]; /* address offset: 0x0014 */ 340bf72c9c9SXuhui Lin }; 341bf72c9c9SXuhui Lin 342bf72c9c9SXuhui Lin check_member(rk3576_ufs_grf_reg, reserved0014, 0x0014); 343bf72c9c9SXuhui Lin 344bf72c9c9SXuhui Lin /* usbdpphy_grf register structure define */ 345bf72c9c9SXuhui Lin struct rk3576_usbdpphy_grf_reg { 346bf72c9c9SXuhui Lin uint32_t reserved0000; /* address offset: 0x0000 */ 347bf72c9c9SXuhui Lin uint32_t con[3]; /* address offset: 0x0004 */ 348bf72c9c9SXuhui Lin uint32_t reserved0010[29]; /* address offset: 0x0010 */ 349bf72c9c9SXuhui Lin uint32_t status[1]; /* address offset: 0x0084 */ 350bf72c9c9SXuhui Lin uint32_t reserved0088[14]; /* address offset: 0x0088 */ 351bf72c9c9SXuhui Lin uint32_t lfps_det_con; /* address offset: 0x00c0 */ 352bf72c9c9SXuhui Lin uint32_t int_en; /* address offset: 0x00c4 */ 353bf72c9c9SXuhui Lin uint32_t int_status; /* address offset: 0x00c8 */ 354bf72c9c9SXuhui Lin }; 355bf72c9c9SXuhui Lin 356bf72c9c9SXuhui Lin check_member(rk3576_usbdpphy_grf_reg, int_status, 0x00c8); 357bf72c9c9SXuhui Lin 358bf72c9c9SXuhui Lin /* usb_grf register structure define */ 359bf72c9c9SXuhui Lin struct rk3576_usb_grf_reg { 360bf72c9c9SXuhui Lin uint32_t mmubp_st; /* address offset: 0x0000 */ 361bf72c9c9SXuhui Lin uint32_t mmubp_con; /* address offset: 0x0004 */ 362bf72c9c9SXuhui Lin uint32_t mmu2_con; /* address offset: 0x0008 */ 363bf72c9c9SXuhui Lin uint32_t mem_con0; /* address offset: 0x000c */ 364bf72c9c9SXuhui Lin uint32_t mem_con1; /* address offset: 0x0010 */ 365bf72c9c9SXuhui Lin uint32_t reserved0014[2]; /* address offset: 0x0014 */ 366bf72c9c9SXuhui Lin uint32_t usb3otg0_status_lat[2]; /* address offset: 0x001c */ 367bf72c9c9SXuhui Lin uint32_t usb3otg0_status_cb; /* address offset: 0x0024 */ 368bf72c9c9SXuhui Lin uint32_t usb3otg0_status; /* address offset: 0x0028 */ 369bf72c9c9SXuhui Lin uint32_t usb3otg0_con[2]; /* address offset: 0x002c */ 370bf72c9c9SXuhui Lin uint32_t reserved0034[4]; /* address offset: 0x0034 */ 371bf72c9c9SXuhui Lin uint32_t mmu2_st[5]; /* address offset: 0x0044 */ 372bf72c9c9SXuhui Lin uint32_t mem_con[1]; /* address offset: 0x0058 */ 373bf72c9c9SXuhui Lin }; 374bf72c9c9SXuhui Lin 375bf72c9c9SXuhui Lin check_member(rk3576_usb_grf_reg, mem_con, 0x0058); 376bf72c9c9SXuhui Lin 377bf72c9c9SXuhui Lin /* vo0_grf register structure define */ 378bf72c9c9SXuhui Lin struct rk3576_vo0_grf_reg { 379bf72c9c9SXuhui Lin uint32_t soc_con[34]; /* address offset: 0x0000 */ 380bf72c9c9SXuhui Lin uint32_t reserved0088[14]; /* address offset: 0x0088 */ 381bf72c9c9SXuhui Lin uint32_t soc_st[6]; /* address offset: 0x00c0 */ 382bf72c9c9SXuhui Lin uint32_t reserved00d8[6]; /* address offset: 0x00d8 */ 383bf72c9c9SXuhui Lin uint32_t hdcp0_rng_con[1]; /* address offset: 0x00f0 */ 384bf72c9c9SXuhui Lin uint32_t reserved00f4; /* address offset: 0x00f4 */ 385bf72c9c9SXuhui Lin uint32_t hdcp0_rng_st[1]; /* address offset: 0x00f8 */ 386bf72c9c9SXuhui Lin }; 387bf72c9c9SXuhui Lin 388bf72c9c9SXuhui Lin check_member(rk3576_vo0_grf_reg, hdcp0_rng_st, 0x00f8); 389bf72c9c9SXuhui Lin 390bf72c9c9SXuhui Lin /* vo1_grf register structure define */ 391bf72c9c9SXuhui Lin struct rk3576_vo1_grf_reg { 392bf72c9c9SXuhui Lin uint32_t soc_con[35]; /* address offset: 0x0000 */ 393bf72c9c9SXuhui Lin uint32_t reserved008c[13]; /* address offset: 0x008c */ 394bf72c9c9SXuhui Lin uint32_t soc_st[3]; /* address offset: 0x00c0 */ 395bf72c9c9SXuhui Lin uint32_t reserved00cc[9]; /* address offset: 0x00cc */ 396bf72c9c9SXuhui Lin uint32_t hdcp1_rng_con[1]; /* address offset: 0x00f0 */ 397bf72c9c9SXuhui Lin uint32_t reserved00f4; /* address offset: 0x00f4 */ 398bf72c9c9SXuhui Lin uint32_t hdcp1_rng_st[1]; /* address offset: 0x00f8 */ 399bf72c9c9SXuhui Lin }; 400bf72c9c9SXuhui Lin 401bf72c9c9SXuhui Lin check_member(rk3576_vo1_grf_reg, hdcp1_rng_st, 0x00f8); 402bf72c9c9SXuhui Lin 403bf72c9c9SXuhui Lin /* vop_grf register structure define */ 404bf72c9c9SXuhui Lin struct rk3576_vop_grf_reg { 405bf72c9c9SXuhui Lin uint32_t reserved0000; /* address offset: 0x0000 */ 406bf72c9c9SXuhui Lin uint32_t soc_con[3]; /* address offset: 0x0004 */ 407bf72c9c9SXuhui Lin }; 408bf72c9c9SXuhui Lin 409bf72c9c9SXuhui Lin check_member(rk3576_vop_grf_reg, soc_con, 0x0004); 410bf72c9c9SXuhui Lin 411bf72c9c9SXuhui Lin #endif /* _ASM_ARCH_GRF_RK3576_H */ 412