1bf72c9c9SXuhui Lin /* 2bf72c9c9SXuhui Lin * (C) Copyright 2021 Rockchip Electronics Co., Ltd. 3bf72c9c9SXuhui Lin * 4bf72c9c9SXuhui Lin * SPDX-License-Identifier: GPL-2.0+ 5bf72c9c9SXuhui Lin */ 6bf72c9c9SXuhui Lin #ifndef _ASM_ARCH_IOC_RK3576_H 7bf72c9c9SXuhui Lin #define _ASM_ARCH_IOC_RK3576_H 8bf72c9c9SXuhui Lin 9bf72c9c9SXuhui Lin #include <common.h> 10bf72c9c9SXuhui Lin 11bf72c9c9SXuhui Lin /* pmu0_ioc register structure define */ 12bf72c9c9SXuhui Lin struct rk3576_pmu0_ioc_reg { 13bf72c9c9SXuhui Lin uint32_t gpio0a_iomux_sel_l; /* address offset: 0x0000 */ 14bf72c9c9SXuhui Lin uint32_t gpio0a_iomux_sel_h; /* address offset: 0x0004 */ 15bf72c9c9SXuhui Lin uint32_t gpio0b_iomux_sel_l; /* address offset: 0x0008 */ 16bf72c9c9SXuhui Lin uint32_t reserved000c; /* address offset: 0x000c */ 17bf72c9c9SXuhui Lin uint32_t gpio0a_ds_l; /* address offset: 0x0010 */ 18bf72c9c9SXuhui Lin uint32_t gpio0a_ds_h; /* address offset: 0x0014 */ 19bf72c9c9SXuhui Lin uint32_t gpio0b_ds_l; /* address offset: 0x0018 */ 20bf72c9c9SXuhui Lin uint32_t reserved001c; /* address offset: 0x001c */ 21bf72c9c9SXuhui Lin uint32_t gpio0a_pull; /* address offset: 0x0020 */ 22bf72c9c9SXuhui Lin uint32_t gpio0b_pull_l; /* address offset: 0x0024 */ 23bf72c9c9SXuhui Lin uint32_t gpio0a_ie; /* address offset: 0x0028 */ 24bf72c9c9SXuhui Lin uint32_t gpio0b_ie_l; /* address offset: 0x002c */ 25bf72c9c9SXuhui Lin uint32_t gpio0a_smt; /* address offset: 0x0030 */ 26bf72c9c9SXuhui Lin uint32_t gpio0b_smt_l; /* address offset: 0x0034 */ 27bf72c9c9SXuhui Lin uint32_t gpio0a_pdis; /* address offset: 0x0038 */ 28bf72c9c9SXuhui Lin uint32_t gpio0b_pdis_l; /* address offset: 0x003c */ 29bf72c9c9SXuhui Lin uint32_t osc_con; /* address offset: 0x0040 */ 30bf72c9c9SXuhui Lin }; 31bf72c9c9SXuhui Lin 32bf72c9c9SXuhui Lin check_member(rk3576_pmu0_ioc_reg, osc_con, 0x0040); 33bf72c9c9SXuhui Lin 34bf72c9c9SXuhui Lin /* pmu1_ioc register structure define */ 35bf72c9c9SXuhui Lin struct rk3576_pmu1_ioc_reg { 36bf72c9c9SXuhui Lin uint32_t gpio0b_iomux_sel_h; /* address offset: 0x0000 */ 37bf72c9c9SXuhui Lin uint32_t gpio0c_iomux_sel_l; /* address offset: 0x0004 */ 38bf72c9c9SXuhui Lin uint32_t gpio0c_iomux_sel_h; /* address offset: 0x0008 */ 39bf72c9c9SXuhui Lin uint32_t gpio0d_iomux_sel_l; /* address offset: 0x000c */ 40bf72c9c9SXuhui Lin uint32_t gpio0d_iomux_sel_h; /* address offset: 0x0010 */ 41bf72c9c9SXuhui Lin uint32_t gpio0b_ds_h; /* address offset: 0x0014 */ 42bf72c9c9SXuhui Lin uint32_t gpio0c_ds_l; /* address offset: 0x0018 */ 43bf72c9c9SXuhui Lin uint32_t gpio0c_ds_h; /* address offset: 0x001c */ 44bf72c9c9SXuhui Lin uint32_t gpio0d_ds_l; /* address offset: 0x0020 */ 45bf72c9c9SXuhui Lin uint32_t gpio0d_ds_h; /* address offset: 0x0024 */ 46bf72c9c9SXuhui Lin uint32_t gpio0b_pull_h; /* address offset: 0x0028 */ 47bf72c9c9SXuhui Lin uint32_t gpio0c_pull; /* address offset: 0x002c */ 48bf72c9c9SXuhui Lin uint32_t gpio0d_pull; /* address offset: 0x0030 */ 49bf72c9c9SXuhui Lin uint32_t gpio0b_ie_h; /* address offset: 0x0034 */ 50bf72c9c9SXuhui Lin uint32_t gpio0c_ie; /* address offset: 0x0038 */ 51bf72c9c9SXuhui Lin uint32_t gpio0d_ie; /* address offset: 0x003c */ 52bf72c9c9SXuhui Lin uint32_t gpio0b_smt_h; /* address offset: 0x0040 */ 53bf72c9c9SXuhui Lin uint32_t gpio0c_smt; /* address offset: 0x0044 */ 54bf72c9c9SXuhui Lin uint32_t gpio0d_smt; /* address offset: 0x0048 */ 55bf72c9c9SXuhui Lin uint32_t gpio0b_pdis_h; /* address offset: 0x004c */ 56bf72c9c9SXuhui Lin uint32_t gpio0c_pdis; /* address offset: 0x0050 */ 57bf72c9c9SXuhui Lin uint32_t gpio0d_pdis; /* address offset: 0x0054 */ 58bf72c9c9SXuhui Lin }; 59bf72c9c9SXuhui Lin 60bf72c9c9SXuhui Lin check_member(rk3576_pmu1_ioc_reg, gpio0d_pdis, 0x0054); 61bf72c9c9SXuhui Lin 62bf72c9c9SXuhui Lin /* top_ioc register structure define */ 63bf72c9c9SXuhui Lin struct rk3576_top_ioc_reg { 64bf72c9c9SXuhui Lin uint32_t reserved0000[2]; /* address offset: 0x0000 */ 65bf72c9c9SXuhui Lin uint32_t gpio0b_iomux_sel_l; /* address offset: 0x0008 */ 66bf72c9c9SXuhui Lin uint32_t gpio0b_iomux_sel_h; /* address offset: 0x000c */ 67bf72c9c9SXuhui Lin uint32_t gpio0c_iomux_sel_l; /* address offset: 0x0010 */ 68bf72c9c9SXuhui Lin uint32_t gpio0c_iomux_sel_h; /* address offset: 0x0014 */ 69bf72c9c9SXuhui Lin uint32_t gpio0d_iomux_sel_l; /* address offset: 0x0018 */ 70bf72c9c9SXuhui Lin uint32_t gpio0d_iomux_sel_h; /* address offset: 0x001c */ 71bf72c9c9SXuhui Lin uint32_t gpio1a_iomux_sel_l; /* address offset: 0x0020 */ 72bf72c9c9SXuhui Lin uint32_t gpio1a_iomux_sel_h; /* address offset: 0x0024 */ 73bf72c9c9SXuhui Lin uint32_t gpio1b_iomux_sel_l; /* address offset: 0x0028 */ 74bf72c9c9SXuhui Lin uint32_t gpio1b_iomux_sel_h; /* address offset: 0x002c */ 75bf72c9c9SXuhui Lin uint32_t gpio1c_iomux_sel_l; /* address offset: 0x0030 */ 76bf72c9c9SXuhui Lin uint32_t gpio1c_iomux_sel_h; /* address offset: 0x0034 */ 77bf72c9c9SXuhui Lin uint32_t gpio1d_iomux_sel_l; /* address offset: 0x0038 */ 78bf72c9c9SXuhui Lin uint32_t gpio1d_iomux_sel_h; /* address offset: 0x003c */ 79bf72c9c9SXuhui Lin uint32_t gpio2a_iomux_sel_l; /* address offset: 0x0040 */ 80bf72c9c9SXuhui Lin uint32_t gpio2a_iomux_sel_h; /* address offset: 0x0044 */ 81bf72c9c9SXuhui Lin uint32_t gpio2b_iomux_sel_l; /* address offset: 0x0048 */ 82bf72c9c9SXuhui Lin uint32_t gpio2b_iomux_sel_h; /* address offset: 0x004c */ 83bf72c9c9SXuhui Lin uint32_t gpio2c_iomux_sel_l; /* address offset: 0x0050 */ 84bf72c9c9SXuhui Lin uint32_t gpio2c_iomux_sel_h; /* address offset: 0x0054 */ 85bf72c9c9SXuhui Lin uint32_t gpio2d_iomux_sel_l; /* address offset: 0x0058 */ 86bf72c9c9SXuhui Lin uint32_t gpio2d_iomux_sel_h; /* address offset: 0x005c */ 87bf72c9c9SXuhui Lin uint32_t gpio3a_iomux_sel_l; /* address offset: 0x0060 */ 88bf72c9c9SXuhui Lin uint32_t gpio3a_iomux_sel_h; /* address offset: 0x0064 */ 89bf72c9c9SXuhui Lin uint32_t gpio3b_iomux_sel_l; /* address offset: 0x0068 */ 90bf72c9c9SXuhui Lin uint32_t gpio3b_iomux_sel_h; /* address offset: 0x006c */ 91bf72c9c9SXuhui Lin uint32_t gpio3c_iomux_sel_l; /* address offset: 0x0070 */ 92bf72c9c9SXuhui Lin uint32_t gpio3c_iomux_sel_h; /* address offset: 0x0074 */ 93bf72c9c9SXuhui Lin uint32_t gpio3d_iomux_sel_l; /* address offset: 0x0078 */ 94bf72c9c9SXuhui Lin uint32_t gpio3d_iomux_sel_h; /* address offset: 0x007c */ 95bf72c9c9SXuhui Lin uint32_t gpio4a_iomux_sel_l; /* address offset: 0x0080 */ 96bf72c9c9SXuhui Lin uint32_t gpio4a_iomux_sel_h; /* address offset: 0x0084 */ 97bf72c9c9SXuhui Lin uint32_t gpio4b_iomux_sel_l; /* address offset: 0x0088 */ 98bf72c9c9SXuhui Lin uint32_t gpio4b_iomux_sel_h; /* address offset: 0x008c */ 99bf72c9c9SXuhui Lin uint32_t reserved0090[24]; /* address offset: 0x0090 */ 100bf72c9c9SXuhui Lin uint32_t ioc_misc_con; /* address offset: 0x00f0 */ 101bf72c9c9SXuhui Lin uint32_t sdmmc_detn_flt; /* address offset: 0x00f4 */ 102bf72c9c9SXuhui Lin }; 103bf72c9c9SXuhui Lin 104bf72c9c9SXuhui Lin check_member(rk3576_top_ioc_reg, sdmmc_detn_flt, 0x00f4); 105bf72c9c9SXuhui Lin 106*3bb83c7fSXuhui Lin /* vccio_ioc register structure define */ 107*3bb83c7fSXuhui Lin struct rk3576_vccio_ioc_reg { 108*3bb83c7fSXuhui Lin uint32_t reserved0000[8]; /* address offset: 0x0000 */ 109*3bb83c7fSXuhui Lin uint32_t gpio1a_ds_l; /* address offset: 0x0020 */ 110*3bb83c7fSXuhui Lin uint32_t gpio1a_ds_h; /* address offset: 0x0024 */ 111*3bb83c7fSXuhui Lin uint32_t gpio1b_ds_l; /* address offset: 0x0028 */ 112*3bb83c7fSXuhui Lin uint32_t gpio1b_ds_h; /* address offset: 0x002c */ 113*3bb83c7fSXuhui Lin uint32_t gpio1c_ds_l; /* address offset: 0x0030 */ 114*3bb83c7fSXuhui Lin uint32_t gpio1c_ds_h; /* address offset: 0x0034 */ 115*3bb83c7fSXuhui Lin uint32_t gpio1d_ds_l; /* address offset: 0x0038 */ 116*3bb83c7fSXuhui Lin uint32_t gpio1d_ds_h; /* address offset: 0x003c */ 117*3bb83c7fSXuhui Lin uint32_t gpio2a_ds_l; /* address offset: 0x0040 */ 118*3bb83c7fSXuhui Lin uint32_t gpio2a_ds_h; /* address offset: 0x0044 */ 119*3bb83c7fSXuhui Lin uint32_t gpio2b_ds_l; /* address offset: 0x0048 */ 120*3bb83c7fSXuhui Lin uint32_t gpio2b_ds_h; /* address offset: 0x004c */ 121*3bb83c7fSXuhui Lin uint32_t gpio2c_ds_l; /* address offset: 0x0050 */ 122*3bb83c7fSXuhui Lin uint32_t gpio2c_ds_h; /* address offset: 0x0054 */ 123*3bb83c7fSXuhui Lin uint32_t gpio2d_ds_l; /* address offset: 0x0058 */ 124*3bb83c7fSXuhui Lin uint32_t gpio2d_ds_h; /* address offset: 0x005c */ 125*3bb83c7fSXuhui Lin uint32_t gpio3a_ds_l; /* address offset: 0x0060 */ 126*3bb83c7fSXuhui Lin uint32_t gpio3a_ds_h; /* address offset: 0x0064 */ 127*3bb83c7fSXuhui Lin uint32_t gpio3b_ds_l; /* address offset: 0x0068 */ 128*3bb83c7fSXuhui Lin uint32_t gpio3b_ds_h; /* address offset: 0x006c */ 129*3bb83c7fSXuhui Lin uint32_t gpio3c_ds_l; /* address offset: 0x0070 */ 130*3bb83c7fSXuhui Lin uint32_t gpio3c_ds_h; /* address offset: 0x0074 */ 131*3bb83c7fSXuhui Lin uint32_t gpio3d_ds_l; /* address offset: 0x0078 */ 132*3bb83c7fSXuhui Lin uint32_t gpio3d_ds_h; /* address offset: 0x007c */ 133*3bb83c7fSXuhui Lin uint32_t gpio4a_ds_l; /* address offset: 0x0080 */ 134*3bb83c7fSXuhui Lin uint32_t gpio4a_ds_h; /* address offset: 0x0084 */ 135*3bb83c7fSXuhui Lin uint32_t gpio4b_ds_l; /* address offset: 0x0088 */ 136*3bb83c7fSXuhui Lin uint32_t gpio4b_ds_h; /* address offset: 0x008c */ 137*3bb83c7fSXuhui Lin uint32_t reserved0090[32]; /* address offset: 0x0090 */ 138*3bb83c7fSXuhui Lin uint32_t gpio1a_pull; /* address offset: 0x0110 */ 139*3bb83c7fSXuhui Lin uint32_t gpio1b_pull; /* address offset: 0x0114 */ 140*3bb83c7fSXuhui Lin uint32_t gpio1c_pull; /* address offset: 0x0118 */ 141*3bb83c7fSXuhui Lin uint32_t gpio1d_pull; /* address offset: 0x011c */ 142*3bb83c7fSXuhui Lin uint32_t gpio2a_pull; /* address offset: 0x0120 */ 143*3bb83c7fSXuhui Lin uint32_t gpio2b_pull; /* address offset: 0x0124 */ 144*3bb83c7fSXuhui Lin uint32_t gpio2c_pull; /* address offset: 0x0128 */ 145*3bb83c7fSXuhui Lin uint32_t gpio2d_pull; /* address offset: 0x012c */ 146*3bb83c7fSXuhui Lin uint32_t gpio3a_pull; /* address offset: 0x0130 */ 147*3bb83c7fSXuhui Lin uint32_t gpio3b_pull; /* address offset: 0x0134 */ 148*3bb83c7fSXuhui Lin uint32_t gpio3c_pull; /* address offset: 0x0138 */ 149*3bb83c7fSXuhui Lin uint32_t gpio3d_pull; /* address offset: 0x013c */ 150*3bb83c7fSXuhui Lin uint32_t gpio4a_pull; /* address offset: 0x0140 */ 151*3bb83c7fSXuhui Lin uint32_t gpio4b_pull; /* address offset: 0x0144 */ 152*3bb83c7fSXuhui Lin uint32_t reserved0148[14]; /* address offset: 0x0148 */ 153*3bb83c7fSXuhui Lin uint32_t gpio1a_ie; /* address offset: 0x0180 */ 154*3bb83c7fSXuhui Lin uint32_t gpio1b_ie; /* address offset: 0x0184 */ 155*3bb83c7fSXuhui Lin uint32_t gpio1c_ie; /* address offset: 0x0188 */ 156*3bb83c7fSXuhui Lin uint32_t gpio1d_ie; /* address offset: 0x018c */ 157*3bb83c7fSXuhui Lin uint32_t gpio2a_ie; /* address offset: 0x0190 */ 158*3bb83c7fSXuhui Lin uint32_t gpio2b_ie; /* address offset: 0x0194 */ 159*3bb83c7fSXuhui Lin uint32_t gpio2c_ie; /* address offset: 0x0198 */ 160*3bb83c7fSXuhui Lin uint32_t gpio2d_ie; /* address offset: 0x019c */ 161*3bb83c7fSXuhui Lin uint32_t gpio3a_ie; /* address offset: 0x01a0 */ 162*3bb83c7fSXuhui Lin uint32_t gpio3b_ie; /* address offset: 0x01a4 */ 163*3bb83c7fSXuhui Lin uint32_t gpio3c_ie; /* address offset: 0x01a8 */ 164*3bb83c7fSXuhui Lin uint32_t gpio3d_ie; /* address offset: 0x01ac */ 165*3bb83c7fSXuhui Lin uint32_t gpio4a_ie; /* address offset: 0x01b0 */ 166*3bb83c7fSXuhui Lin uint32_t gpio4b_ie; /* address offset: 0x01b4 */ 167*3bb83c7fSXuhui Lin uint32_t reserved01b8[22]; /* address offset: 0x01b8 */ 168*3bb83c7fSXuhui Lin uint32_t gpio1a_smt; /* address offset: 0x0210 */ 169*3bb83c7fSXuhui Lin uint32_t gpio1b_smt; /* address offset: 0x0214 */ 170*3bb83c7fSXuhui Lin uint32_t gpio1c_smt; /* address offset: 0x0218 */ 171*3bb83c7fSXuhui Lin uint32_t gpio1d_smt; /* address offset: 0x021c */ 172*3bb83c7fSXuhui Lin uint32_t gpio2a_smt; /* address offset: 0x0220 */ 173*3bb83c7fSXuhui Lin uint32_t gpio2b_smt; /* address offset: 0x0224 */ 174*3bb83c7fSXuhui Lin uint32_t gpio2c_smt; /* address offset: 0x0228 */ 175*3bb83c7fSXuhui Lin uint32_t gpio2d_smt; /* address offset: 0x022c */ 176*3bb83c7fSXuhui Lin uint32_t gpio3a_smt; /* address offset: 0x0230 */ 177*3bb83c7fSXuhui Lin uint32_t gpio3b_smt; /* address offset: 0x0234 */ 178*3bb83c7fSXuhui Lin uint32_t gpio3c_smt; /* address offset: 0x0238 */ 179*3bb83c7fSXuhui Lin uint32_t gpio3d_smt; /* address offset: 0x023c */ 180*3bb83c7fSXuhui Lin uint32_t gpio4a_smt; /* address offset: 0x0240 */ 181*3bb83c7fSXuhui Lin uint32_t gpio4b_smt; /* address offset: 0x0244 */ 182*3bb83c7fSXuhui Lin uint32_t reserved0248[14]; /* address offset: 0x0248 */ 183*3bb83c7fSXuhui Lin uint32_t gpio1a_pdis; /* address offset: 0x0280 */ 184*3bb83c7fSXuhui Lin uint32_t gpio1b_pdis; /* address offset: 0x0284 */ 185*3bb83c7fSXuhui Lin uint32_t gpio1c_pdis; /* address offset: 0x0288 */ 186*3bb83c7fSXuhui Lin uint32_t gpio1d_pdis; /* address offset: 0x028c */ 187*3bb83c7fSXuhui Lin uint32_t gpio2a_pdis; /* address offset: 0x0290 */ 188*3bb83c7fSXuhui Lin uint32_t gpio2b_pdis; /* address offset: 0x0294 */ 189*3bb83c7fSXuhui Lin uint32_t gpio2c_pdis; /* address offset: 0x0298 */ 190*3bb83c7fSXuhui Lin uint32_t gpio2d_pdis; /* address offset: 0x029c */ 191*3bb83c7fSXuhui Lin uint32_t gpio3a_pdis; /* address offset: 0x02a0 */ 192*3bb83c7fSXuhui Lin uint32_t gpio3b_pdis; /* address offset: 0x02a4 */ 193*3bb83c7fSXuhui Lin uint32_t gpio3c_pdis; /* address offset: 0x02a8 */ 194*3bb83c7fSXuhui Lin uint32_t gpio3d_pdis; /* address offset: 0x02ac */ 195*3bb83c7fSXuhui Lin uint32_t gpio4a_pdis; /* address offset: 0x02b0 */ 196*3bb83c7fSXuhui Lin uint32_t gpio4b_pdis; /* address offset: 0x02b4 */ 197*3bb83c7fSXuhui Lin uint32_t reserved02b8[82]; /* address offset: 0x02b8 */ 198*3bb83c7fSXuhui Lin uint32_t misc_con[9]; /* address offset: 0x0400 */ 199*3bb83c7fSXuhui Lin }; 200*3bb83c7fSXuhui Lin 201*3bb83c7fSXuhui Lin check_member(rk3576_vccio_ioc_reg, misc_con, 0x0400); 202*3bb83c7fSXuhui Lin 203*3bb83c7fSXuhui Lin /* vccio6_ioc register structure define */ 204*3bb83c7fSXuhui Lin struct rk3576_vccio6_ioc_reg { 205*3bb83c7fSXuhui Lin uint32_t reserved0000[36]; /* address offset: 0x0000 */ 206*3bb83c7fSXuhui Lin uint32_t gpio4c_ds_l; /* address offset: 0x0090 */ 207*3bb83c7fSXuhui Lin uint32_t gpio4c_ds_h; /* address offset: 0x0094 */ 208*3bb83c7fSXuhui Lin uint32_t reserved0098[44]; /* address offset: 0x0098 */ 209*3bb83c7fSXuhui Lin uint32_t gpio4c_pull; /* address offset: 0x0148 */ 210*3bb83c7fSXuhui Lin uint32_t reserved014c[27]; /* address offset: 0x014c */ 211*3bb83c7fSXuhui Lin uint32_t gpio4c_ie; /* address offset: 0x01b8 */ 212*3bb83c7fSXuhui Lin uint32_t reserved01bc[35]; /* address offset: 0x01bc */ 213*3bb83c7fSXuhui Lin uint32_t gpio4c_smt; /* address offset: 0x0248 */ 214*3bb83c7fSXuhui Lin uint32_t reserved024c[27]; /* address offset: 0x024c */ 215*3bb83c7fSXuhui Lin uint32_t gpio4c_pdis; /* address offset: 0x02b8 */ 216*3bb83c7fSXuhui Lin uint32_t reserved02bc[53]; /* address offset: 0x02bc */ 217*3bb83c7fSXuhui Lin uint32_t gpio4c_iomux_sel_l; /* address offset: 0x0390 */ 218*3bb83c7fSXuhui Lin uint32_t gpio4c_iomux_sel_h; /* address offset: 0x0394 */ 219*3bb83c7fSXuhui Lin uint32_t reserved0398[26]; /* address offset: 0x0398 */ 220*3bb83c7fSXuhui Lin uint32_t misc_con[2]; /* address offset: 0x0400 */ 221*3bb83c7fSXuhui Lin uint32_t reserved0408[14]; /* address offset: 0x0408 */ 222*3bb83c7fSXuhui Lin uint32_t hdmitx_hpd_status; /* address offset: 0x0440 */ 223*3bb83c7fSXuhui Lin }; 224*3bb83c7fSXuhui Lin 225*3bb83c7fSXuhui Lin check_member(rk3576_vccio6_ioc_reg, hdmitx_hpd_status, 0x0440); 226*3bb83c7fSXuhui Lin 227*3bb83c7fSXuhui Lin /* vccio7_ioc register structure define */ 228*3bb83c7fSXuhui Lin struct rk3576_vccio7_ioc_reg { 229*3bb83c7fSXuhui Lin uint32_t reserved0000[38]; /* address offset: 0x0000 */ 230*3bb83c7fSXuhui Lin uint32_t gpio4d_ds_l; /* address offset: 0x0098 */ 231*3bb83c7fSXuhui Lin uint32_t reserved009c[44]; /* address offset: 0x009c */ 232*3bb83c7fSXuhui Lin uint32_t gpio4d_pull; /* address offset: 0x014c */ 233*3bb83c7fSXuhui Lin uint32_t reserved0150[27]; /* address offset: 0x0150 */ 234*3bb83c7fSXuhui Lin uint32_t gpio4d_ie; /* address offset: 0x01bc */ 235*3bb83c7fSXuhui Lin uint32_t reserved01c0[35]; /* address offset: 0x01c0 */ 236*3bb83c7fSXuhui Lin uint32_t gpio4d_smt; /* address offset: 0x024c */ 237*3bb83c7fSXuhui Lin uint32_t reserved0250[27]; /* address offset: 0x0250 */ 238*3bb83c7fSXuhui Lin uint32_t gpio4d_pdis; /* address offset: 0x02bc */ 239*3bb83c7fSXuhui Lin uint32_t reserved02c0[54]; /* address offset: 0x02c0 */ 240*3bb83c7fSXuhui Lin uint32_t gpio4d_iomux_sel_l; /* address offset: 0x0398 */ 241*3bb83c7fSXuhui Lin uint32_t reserved039c[25]; /* address offset: 0x039c */ 242*3bb83c7fSXuhui Lin uint32_t xin_ufs_con; /* address offset: 0x0400 */ 243*3bb83c7fSXuhui Lin }; 244*3bb83c7fSXuhui Lin 245*3bb83c7fSXuhui Lin check_member(rk3576_vccio7_ioc_reg, xin_ufs_con, 0x0400); 246*3bb83c7fSXuhui Lin 247bf72c9c9SXuhui Lin #endif /* _ASM_ARCH_IOC_RK3576_H */ 248