1c6f7c1a3SJoseph Chen /* 2c6f7c1a3SJoseph Chen * (C) Copyright 2022 Rockchip Electronics Co., Ltd. 3c6f7c1a3SJoseph Chen * 4c6f7c1a3SJoseph Chen * SPDX-License-Identifier: GPL-2.0+ 5c6f7c1a3SJoseph Chen */ 6c6f7c1a3SJoseph Chen #ifndef _ASM_ARCH_GRF_RK3528_H 7c6f7c1a3SJoseph Chen #define _ASM_ARCH_GRF_RK3528_H 8c6f7c1a3SJoseph Chen 9c6f7c1a3SJoseph Chen #include <common.h> 10c6f7c1a3SJoseph Chen 11c6f7c1a3SJoseph Chen struct rk3528_grf { 12*c563400aSDavid Wu uint32_t reserved0[0x40018 / 4]; 13*c563400aSDavid Wu 14*c563400aSDavid Wu /* vpugrf*/ 15*c563400aSDavid Wu uint32_t gmac1_con0; /* Address Offset: 0x40018 */ 16*c563400aSDavid Wu uint32_t gmac1_con1; /* Address Offset: 0x4001c */ 17*c563400aSDavid Wu uint32_t reserved1[(0x60018 - 0x4001c) / 4 - 1]; 18c6f7c1a3SJoseph Chen 19c6f7c1a3SJoseph Chen /* vogrf */ 20*c563400aSDavid Wu uint32_t gmac0_con; /* Address Offset: 0x60018 */ 21*c563400aSDavid Wu uint32_t macphy_con0; /* Address Offset: 0x6001c */ 22*c563400aSDavid Wu uint32_t macphy_con1; /* Address Offset: 0x60020 */ 23*c563400aSDavid Wu uint32_t sdmmc_con0; /* Address Offset: 0x60024 */ 24c6f7c1a3SJoseph Chen uint32_t sdmmc_con1; /* Address Offset: 0x60028 */ 25*c563400aSDavid Wu uint32_t reserved2[(0x70000 - 0x60028) / 4 - 1]; 26c6f7c1a3SJoseph Chen 27c6f7c1a3SJoseph Chen /* pmugrf */ 28c6f7c1a3SJoseph Chen uint32_t soc_con[8]; /* Address Offset: 0x70000 */ 29c6f7c1a3SJoseph Chen uint32_t soc_status; /* Address Offset: 0x70020 */ 30c6f7c1a3SJoseph Chen uint32_t reserved3[3]; /* Address Offset: 0x70024 */ 31c6f7c1a3SJoseph Chen uint32_t pmuio_vsel; /* Address Offset: 0x70030 */ 32c6f7c1a3SJoseph Chen uint32_t reserved4[3]; /* Address Offset: 0x70034 */ 33c6f7c1a3SJoseph Chen uint32_t mem_con; /* Address Offset: 0x70040 */ 34c6f7c1a3SJoseph Chen uint32_t reserved5[47]; /* Address Offset: 0x70044 */ 35c6f7c1a3SJoseph Chen uint32_t rstfunc_status; /* Address Offset: 0x70100 */ 36c6f7c1a3SJoseph Chen uint32_t rstfunc_clr; /* Address Offset: 0x70104 */ 37c6f7c1a3SJoseph Chen uint32_t reserved6[62]; /* Address Offset: 0x70108 */ 38c6f7c1a3SJoseph Chen uint32_t os_reg0; /* Address Offset: 0x70200 */ 39c6f7c1a3SJoseph Chen uint32_t os_reg1; /* Address Offset: 0x70204 */ 40c6f7c1a3SJoseph Chen uint32_t os_reg2; /* Address Offset: 0x70208 */ 41c6f7c1a3SJoseph Chen uint32_t os_reg3; /* Address Offset: 0x7020C */ 42c6f7c1a3SJoseph Chen uint32_t os_reg4; /* Address Offset: 0x70210 */ 43c6f7c1a3SJoseph Chen uint32_t os_reg5; /* Address Offset: 0x70214 */ 44c6f7c1a3SJoseph Chen uint32_t os_reg6; /* Address Offset: 0x70218 */ 45c6f7c1a3SJoseph Chen uint32_t os_reg7; /* Address Offset: 0x7021C */ 46c6f7c1a3SJoseph Chen uint32_t os_reg8; /* Address Offset: 0x70220 */ 47c6f7c1a3SJoseph Chen uint32_t os_reg9; /* Address Offset: 0x70224 */ 48c6f7c1a3SJoseph Chen uint32_t os_reg10; /* Address Offset: 0x70228 */ 49c6f7c1a3SJoseph Chen uint32_t os_reg11; /* Address Offset: 0x7022C */ 50c6f7c1a3SJoseph Chen uint32_t os_reg12; /* Address Offset: 0x70230 */ 51c6f7c1a3SJoseph Chen uint32_t os_reg13; /* Address Offset: 0x70234 */ 52c6f7c1a3SJoseph Chen uint32_t os_reg14; /* Address Offset: 0x70238 */ 53c6f7c1a3SJoseph Chen uint32_t os_reg15; /* Address Offset: 0x7023C */ 54c6f7c1a3SJoseph Chen uint32_t os_reg16; /* Address Offset: 0x70240 */ 55c6f7c1a3SJoseph Chen uint32_t os_reg17; /* Address Offset: 0x70244 */ 56c6f7c1a3SJoseph Chen uint32_t os_reg18; /* Address Offset: 0x70248 */ 57c6f7c1a3SJoseph Chen uint32_t os_reg19; /* Address Offset: 0x7024C */ 58c6f7c1a3SJoseph Chen uint32_t os_reg20; /* Address Offset: 0x70250 */ 59c6f7c1a3SJoseph Chen uint32_t os_reg21; /* Address Offset: 0x70254 */ 60c6f7c1a3SJoseph Chen uint32_t os_reg22; /* Address Offset: 0x70258 */ 61c6f7c1a3SJoseph Chen uint32_t os_reg23; /* Address Offset: 0x7025C */ 62c6f7c1a3SJoseph Chen uint32_t reserved7[(0x80000 - 0x7025C) / 4 - 1]; 63c6f7c1a3SJoseph Chen 64c6f7c1a3SJoseph Chen uint32_t grf_sys_con[2]; /* Address Offset: 0x80000 */ 65c6f7c1a3SJoseph Chen uint32_t reserved8[2]; /* Address Offset: 0x80008 */ 66c6f7c1a3SJoseph Chen uint32_t grf_sys_status; /* Address Offset: 0x80010 */ 67c6f7c1a3SJoseph Chen uint32_t reserved9[3]; /* Address Offset: 0x80014 */ 68c6f7c1a3SJoseph Chen uint32_t grf_biu_con[2]; /* Address Offset: 0x80020 */ 69c6f7c1a3SJoseph Chen uint32_t reserved10[2]; /* Address Offset: 0x80028 */ 70c6f7c1a3SJoseph Chen uint32_t grf_biu_status[3]; /* Address Offset: 0x80030 */ 71c6f7c1a3SJoseph Chen uint32_t reserved11[17]; /* Address Offset: 0x8003C */ 72c6f7c1a3SJoseph Chen uint32_t grf_sys_mem_con[5]; /* Address Offset: 0x80080 */ 73c6f7c1a3SJoseph Chen uint32_t reserved12[59]; /* Address Offset: 0x80094 */ 74c6f7c1a3SJoseph Chen uint32_t grf_soc_code; /* Address Offset: 0x80180 */ 75c6f7c1a3SJoseph Chen uint32_t reserved13[3]; /* Address Offset: 0x80184 */ 76c6f7c1a3SJoseph Chen uint32_t grf_soc_version; /* Address Offset: 0x80190 */ 77c6f7c1a3SJoseph Chen uint32_t reserved14[3]; /* Address Offset: 0x80194 */ 78c6f7c1a3SJoseph Chen uint32_t grf_chip_id; /* Address Offset: 0x801A0 */ 79c6f7c1a3SJoseph Chen uint32_t reserved15[3]; /* Address Offset: 0x801A4 */ 80c6f7c1a3SJoseph Chen uint32_t grf_chip_version; /* Address Offset: 0x801B0 */ 81c6f7c1a3SJoseph Chen uint32_t reserved16[(0x10000 - 0x81b0) / 4 - 1]; 82c6f7c1a3SJoseph Chen 83c6f7c1a3SJoseph Chen }; 84c6f7c1a3SJoseph Chen 85c6f7c1a3SJoseph Chen check_member(rk3528_grf, sdmmc_con1, 0x60028); 86c6f7c1a3SJoseph Chen check_member(rk3528_grf, os_reg23, 0x7025C); 87c6f7c1a3SJoseph Chen check_member(rk3528_grf, grf_chip_version, 0x801B0); 88c6f7c1a3SJoseph Chen 89c6f7c1a3SJoseph Chen #endif 90