Lines Matching refs:uint32_t
13 uint32_t gpio0a_iomux_sel_0; /* address offset: 0x0000 */
14 uint32_t gpio0a_iomux_sel_1; /* address offset: 0x0004 */
15 uint32_t gpio0b_iomux_sel_0; /* address offset: 0x0008 */
16 uint32_t gpio0b_iomux_sel_1; /* address offset: 0x000c */
17 uint32_t reserved0010[60]; /* address offset: 0x0010 */
18 uint32_t gpio0a_ds_0; /* address offset: 0x0100 */
19 uint32_t gpio0a_ds_1; /* address offset: 0x0104 */
20 uint32_t gpio0a_ds_2; /* address offset: 0x0108 */
21 uint32_t gpio0a_ds_3; /* address offset: 0x010c */
22 uint32_t gpio0b_ds_0; /* address offset: 0x0110 */
23 uint32_t gpio0b_ds_1; /* address offset: 0x0114 */
24 uint32_t gpio0b_ds_2; /* address offset: 0x0118 */
25 uint32_t reserved011c[121]; /* address offset: 0x011c */
26 uint32_t gpio0a_pull; /* address offset: 0x0300 */
27 uint32_t gpio0b_pull; /* address offset: 0x0304 */
28 uint32_t reserved0308[62]; /* address offset: 0x0308 */
29 uint32_t gpio0a_ie; /* address offset: 0x0400 */
30 uint32_t gpio0b_ie; /* address offset: 0x0404 */
31 uint32_t reserved0408[62]; /* address offset: 0x0408 */
32 uint32_t gpio0a_smt; /* address offset: 0x0500 */
33 uint32_t gpio0b_smt; /* address offset: 0x0504 */
34 uint32_t reserved0508[62]; /* address offset: 0x0508 */
35 uint32_t gpio0a_sus; /* address offset: 0x0600 */
36 uint32_t gpio0b_sus; /* address offset: 0x0604 */
37 uint32_t reserved0608[62]; /* address offset: 0x0608 */
38 uint32_t gpio0a_sl; /* address offset: 0x0700 */
39 uint32_t gpio0b_sl; /* address offset: 0x0704 */
40 uint32_t reserved0708[62]; /* address offset: 0x0708 */
41 uint32_t gpio0a_od; /* address offset: 0x0800 */
42 uint32_t gpio0b_od; /* address offset: 0x0804 */
43 uint32_t reserved0808[62]; /* address offset: 0x0808 */
44 uint32_t io_vsel; /* address offset: 0x0900 */
45 uint32_t grf_jtag_con0; /* address offset: 0x0904 */
46 uint32_t grf_jtag_con1; /* address offset: 0x0908 */
47 uint32_t reserved090c; /* address offset: 0x090c */
48 uint32_t xin_con; /* address offset: 0x0910 */
49 uint32_t reserved0914[187]; /* address offset: 0x0914 */
50 uint32_t grf_gpio0_filter_con0; /* address offset: 0x0c00 */
51 uint32_t grf_gpio0_filter_con1; /* address offset: 0x0c04 */
52 uint32_t grf_gpio0_filter_con2; /* address offset: 0x0c08 */
53 uint32_t grf_gpio0_filter_con3; /* address offset: 0x0c0c */
54 uint32_t grf_gpio0_filter_con4; /* address offset: 0x0c10 */
55 uint32_t grf_gpio0_filter_con5; /* address offset: 0x0c14 */
62 uint32_t reserved0000[4]; /* address offset: 0x0000 */
63 uint32_t gpio0c_iomux_sel_0; /* address offset: 0x0010 */
64 uint32_t gpio0c_iomux_sel_1; /* address offset: 0x0014 */
65 uint32_t gpio0d_iomux_sel_0; /* address offset: 0x0018 */
66 uint32_t reserved001c[65]; /* address offset: 0x001c */
67 uint32_t gpio0c_ds_0; /* address offset: 0x0120 */
68 uint32_t gpio0c_ds_1; /* address offset: 0x0124 */
69 uint32_t gpio0c_ds_2; /* address offset: 0x0128 */
70 uint32_t gpio0c_ds_3; /* address offset: 0x012c */
71 uint32_t gpio0d_ds_0; /* address offset: 0x0130 */
72 uint32_t reserved0134[117]; /* address offset: 0x0134 */
73 uint32_t gpio0c_pull; /* address offset: 0x0308 */
74 uint32_t gpio0d_pull; /* address offset: 0x030c */
75 uint32_t reserved0310[62]; /* address offset: 0x0310 */
76 uint32_t gpio0c_ie; /* address offset: 0x0408 */
77 uint32_t gpio0d_ie; /* address offset: 0x040c */
78 uint32_t reserved0410[62]; /* address offset: 0x0410 */
79 uint32_t gpio0c_smt; /* address offset: 0x0508 */
80 uint32_t gpio0d_smt; /* address offset: 0x050c */
81 uint32_t reserved0510[62]; /* address offset: 0x0510 */
82 uint32_t gpio0c_sus; /* address offset: 0x0608 */
83 uint32_t gpio0d_sus; /* address offset: 0x060c */
84 uint32_t reserved0610[62]; /* address offset: 0x0610 */
85 uint32_t gpio0c_sl; /* address offset: 0x0708 */
86 uint32_t gpio0d_sl; /* address offset: 0x070c */
87 uint32_t reserved0710[62]; /* address offset: 0x0710 */
88 uint32_t gpio0c_od; /* address offset: 0x0808 */
89 uint32_t gpio0d_od; /* address offset: 0x080c */
90 uint32_t reserved0810[60]; /* address offset: 0x0810 */
91 uint32_t io_vsel; /* address offset: 0x0900 */
98 uint32_t reserved0000[8]; /* address offset: 0x0000 */
99 uint32_t gpio1a_iomux_sel_0; /* address offset: 0x0020 */
100 uint32_t gpio1a_iomux_sel_1; /* address offset: 0x0024 */
101 uint32_t gpio1b_iomux_sel_0; /* address offset: 0x0028 */
102 uint32_t gpio1b_iomux_sel_1; /* address offset: 0x002c */
103 uint32_t reserved0030[68]; /* address offset: 0x0030 */
104 uint32_t gpio1a_ds_0; /* address offset: 0x0140 */
105 uint32_t gpio1a_ds_1; /* address offset: 0x0144 */
106 uint32_t gpio1a_ds_2; /* address offset: 0x0148 */
107 uint32_t gpio1a_ds_3; /* address offset: 0x014c */
108 uint32_t gpio1b_ds_0; /* address offset: 0x0150 */
109 uint32_t gpio1b_ds_1; /* address offset: 0x0154 */
110 uint32_t gpio1b_ds_2; /* address offset: 0x0158 */
111 uint32_t gpio1b_ds_3; /* address offset: 0x015c */
112 uint32_t reserved0160[108]; /* address offset: 0x0160 */
113 uint32_t gpio1a_pull; /* address offset: 0x0310 */
114 uint32_t gpio1b_pull; /* address offset: 0x0314 */
115 uint32_t reserved0318[62]; /* address offset: 0x0318 */
116 uint32_t gpio1a_ie; /* address offset: 0x0410 */
117 uint32_t gpio1b_ie; /* address offset: 0x0414 */
118 uint32_t reserved0418[62]; /* address offset: 0x0418 */
119 uint32_t gpio1a_smt; /* address offset: 0x0510 */
120 uint32_t gpio1b_smt; /* address offset: 0x0514 */
121 uint32_t reserved0518[62]; /* address offset: 0x0518 */
122 uint32_t gpio1a_sus; /* address offset: 0x0610 */
123 uint32_t gpio1b_sus; /* address offset: 0x0614 */
124 uint32_t reserved0618[62]; /* address offset: 0x0618 */
125 uint32_t gpio1a_sl; /* address offset: 0x0710 */
126 uint32_t gpio1b_sl; /* address offset: 0x0714 */
127 uint32_t reserved0718[62]; /* address offset: 0x0718 */
128 uint32_t gpio1a_od; /* address offset: 0x0810 */
129 uint32_t gpio1b_od; /* address offset: 0x0814 */
130 uint32_t reserved0818[60]; /* address offset: 0x0818 */
131 uint32_t io1_vsel; /* address offset: 0x0908 */
132 uint32_t reserved090c[61]; /* address offset: 0x090c */
133 uint32_t ioc_misc_con0; /* address offset: 0x0a00 */
134 uint32_t ioc_misc_con1; /* address offset: 0x0a04 */
135 uint32_t ioc_misc_con2; /* address offset: 0x0a08 */
136 uint32_t ioc_misc_con3; /* address offset: 0x0a0c */
137 uint32_t ioc_misc_con4; /* address offset: 0x0a10 */
138 uint32_t ioc_misc_con5; /* address offset: 0x0a14 */
139 uint32_t ioc_misc_con6; /* address offset: 0x0a18 */
146 uint32_t reserved0000[16]; /* address offset: 0x0000 */
147 uint32_t gpio2a_iomux_sel_0; /* address offset: 0x0040 */
148 uint32_t gpio2a_iomux_sel_1; /* address offset: 0x0044 */
149 uint32_t reserved0048[78]; /* address offset: 0x0048 */
150 uint32_t gpio2a_ds_0; /* address offset: 0x0180 */
151 uint32_t gpio2a_ds_1; /* address offset: 0x0184 */
152 uint32_t gpio2a_ds_2; /* address offset: 0x0188 */
153 uint32_t reserved018c[101]; /* address offset: 0x018c */
154 uint32_t gpio2a_pull; /* address offset: 0x0320 */
155 uint32_t reserved0324[63]; /* address offset: 0x0324 */
156 uint32_t gpio2a_ie; /* address offset: 0x0420 */
157 uint32_t reserved0424[63]; /* address offset: 0x0424 */
158 uint32_t gpio2a_smt; /* address offset: 0x0520 */
159 uint32_t reserved0524[63]; /* address offset: 0x0524 */
160 uint32_t gpio2a_sus; /* address offset: 0x0620 */
161 uint32_t reserved0624[63]; /* address offset: 0x0624 */
162 uint32_t gpio2a_sl; /* address offset: 0x0720 */
163 uint32_t reserved0724[63]; /* address offset: 0x0724 */
164 uint32_t gpio2a_od; /* address offset: 0x0820 */
165 uint32_t reserved0824[58]; /* address offset: 0x0824 */
166 uint32_t io_vsel; /* address offset: 0x090c */
167 uint32_t reserved0910[159]; /* address offset: 0x0910 */
168 uint32_t grf_sddet_dly_con; /* address offset: 0x0b8c */
169 uint32_t grf_jtag_con; /* address offset: 0x0b90 */
170 uint32_t reserved0b94[27]; /* address offset: 0x0b94 */
171 uint32_t grf_gpio2_filter_con0; /* address offset: 0x0c00 */
172 uint32_t grf_gpio2_filter_con1; /* address offset: 0x0c04 */
173 uint32_t grf_gpio2_filter_con2; /* address offset: 0x0c08 */
174 uint32_t grf_gpio2_filter_con3; /* address offset: 0x0c0c */
175 uint32_t grf_gpio2_filter_con4; /* address offset: 0x0c10 */
176 uint32_t grf_gpio2_filter_con5; /* address offset: 0x0c14 */
183 uint32_t reserved0000[24]; /* address offset: 0x0000 */
184 uint32_t gpio3a_iomux_sel_0; /* address offset: 0x0060 */
185 uint32_t gpio3a_iomux_sel_1; /* address offset: 0x0064 */
186 uint32_t gpio3b_iomux_sel_0; /* address offset: 0x0068 */
187 uint32_t gpio3b_iomux_sel_1; /* address offset: 0x006c */
188 uint32_t reserved0070[84]; /* address offset: 0x0070 */
189 uint32_t gpio3a_ds_0; /* address offset: 0x01c0 */
190 uint32_t gpio3a_ds_1; /* address offset: 0x01c4 */
191 uint32_t gpio3a_ds_2; /* address offset: 0x01c8 */
192 uint32_t gpio3a_ds_3; /* address offset: 0x01cc */
193 uint32_t gpio3b_ds_0; /* address offset: 0x01d0 */
194 uint32_t gpio3b_ds_1; /* address offset: 0x01d4 */
195 uint32_t gpio3b_ds_2; /* address offset: 0x01d8 */
196 uint32_t gpio3b_ds_3; /* address offset: 0x01dc */
197 uint32_t reserved01e0[84]; /* address offset: 0x01e0 */
198 uint32_t gpio3a_pull; /* address offset: 0x0330 */
199 uint32_t gpio3b_pull; /* address offset: 0x0334 */
200 uint32_t reserved0338[62]; /* address offset: 0x0338 */
201 uint32_t gpio3a_ie; /* address offset: 0x0430 */
202 uint32_t gpio3b_ie; /* address offset: 0x0434 */
203 uint32_t reserved0438[62]; /* address offset: 0x0438 */
204 uint32_t gpio3a_smt; /* address offset: 0x0530 */
205 uint32_t gpio3b_smt; /* address offset: 0x0534 */
206 uint32_t reserved0538[62]; /* address offset: 0x0538 */
207 uint32_t gpio3a_sus; /* address offset: 0x0630 */
208 uint32_t gpio3b_sus; /* address offset: 0x0634 */
209 uint32_t reserved0638[62]; /* address offset: 0x0638 */
210 uint32_t gpio3a_sl; /* address offset: 0x0730 */
211 uint32_t gpio3b_sl; /* address offset: 0x0734 */
212 uint32_t reserved0738[62]; /* address offset: 0x0738 */
213 uint32_t gpio3a_od; /* address offset: 0x0830 */
214 uint32_t gpio3b_od; /* address offset: 0x0834 */
215 uint32_t reserved0838[54]; /* address offset: 0x0838 */
216 uint32_t io3_vsel; /* address offset: 0x0910 */
217 uint32_t reserved0914[59]; /* address offset: 0x0914 */
218 uint32_t ioc_misc_con0; /* address offset: 0x0a00 */
219 uint32_t ioc_misc_con1; /* address offset: 0x0a04 */
220 uint32_t ioc_misc_con2; /* address offset: 0x0a08 */
221 uint32_t ioc_misc_con3; /* address offset: 0x0a0c */
222 uint32_t ioc_misc_con4; /* address offset: 0x0a10 */
223 uint32_t ioc_misc_con5; /* address offset: 0x0a14 */
224 uint32_t ioc_misc_con6; /* address offset: 0x0a18 */
231 uint32_t reserved0000[32]; /* address offset: 0x0000 */
232 uint32_t gpio4a_iomux_sel_0; /* address offset: 0x0080 */
233 uint32_t gpio4a_iomux_sel_1; /* address offset: 0x0084 */
234 uint32_t gpio4b_iomux_sel_0; /* address offset: 0x0088 */
235 uint32_t reserved008c[93]; /* address offset: 0x008c */
236 uint32_t gpio4a_ds_0; /* address offset: 0x0200 */
237 uint32_t gpio4a_ds_1; /* address offset: 0x0204 */
238 uint32_t gpio4a_ds_2; /* address offset: 0x0208 */
239 uint32_t gpio4a_ds_3; /* address offset: 0x020c */
240 uint32_t gpio4b_ds_0; /* address offset: 0x0210 */
241 uint32_t reserved0214[75]; /* address offset: 0x0214 */
242 uint32_t gpio4a_pull; /* address offset: 0x0340 */
243 uint32_t gpio4b_pull; /* address offset: 0x0344 */
244 uint32_t reserved0348[62]; /* address offset: 0x0348 */
245 uint32_t gpio4a_ie; /* address offset: 0x0440 */
246 uint32_t gpio4b_ie; /* address offset: 0x0444 */
247 uint32_t reserved0448[62]; /* address offset: 0x0448 */
248 uint32_t gpio4a_smt; /* address offset: 0x0540 */
249 uint32_t gpio4b_smt; /* address offset: 0x0544 */
250 uint32_t reserved0548[62]; /* address offset: 0x0548 */
251 uint32_t gpio4a_sus; /* address offset: 0x0640 */
252 uint32_t gpio4b_sus; /* address offset: 0x0644 */
253 uint32_t reserved0648[62]; /* address offset: 0x0648 */
254 uint32_t gpio4a_sl; /* address offset: 0x0740 */
255 uint32_t gpio4b_sl; /* address offset: 0x0744 */
256 uint32_t reserved0748[62]; /* address offset: 0x0748 */
257 uint32_t gpio4a_od; /* address offset: 0x0840 */
258 uint32_t gpio4b_od; /* address offset: 0x0844 */
259 uint32_t reserved0848[51]; /* address offset: 0x0848 */
260 uint32_t io_vsel; /* address offset: 0x0914 */
261 uint32_t reserved0918[194]; /* address offset: 0x0918 */
262 uint32_t grf_gpio4_filter_con0; /* address offset: 0x0c20 */
263 uint32_t grf_gpio4_filter_con1; /* address offset: 0x0c24 */
264 uint32_t grf_gpio4_filter_con2; /* address offset: 0x0c28 */
265 uint32_t grf_gpio4_filter_con3; /* address offset: 0x0c2c */
266 uint32_t grf_gpio4_filter_con4; /* address offset: 0x0c30 */
267 uint32_t grf_gpio4_filter_con5; /* address offset: 0x0c34 */
274 uint32_t reserved0000[40]; /* address offset: 0x0000 */
275 uint32_t gpio5a_iomux_sel_0; /* address offset: 0x00a0 */
276 uint32_t gpio5a_iomux_sel_1; /* address offset: 0x00a4 */
277 uint32_t gpio5b_iomux_sel_0; /* address offset: 0x00a8 */
278 uint32_t gpio5b_iomux_sel_1; /* address offset: 0x00ac */
279 uint32_t gpio5c_iomux_sel_0; /* address offset: 0x00b0 */
280 uint32_t gpio5c_iomux_sel_1; /* address offset: 0x00b4 */
281 uint32_t gpio5d_iomux_sel_0; /* address offset: 0x00b8 */
282 uint32_t gpio5d_iomux_sel_1; /* address offset: 0x00bc */
283 uint32_t reserved00c0[96]; /* address offset: 0x00c0 */
284 uint32_t gpio5a_ds_0; /* address offset: 0x0240 */
285 uint32_t gpio5a_ds_1; /* address offset: 0x0244 */
286 uint32_t gpio5a_ds_2; /* address offset: 0x0248 */
287 uint32_t gpio5a_ds_3; /* address offset: 0x024c */
288 uint32_t gpio5b_ds_0; /* address offset: 0x0250 */
289 uint32_t gpio5b_ds_1; /* address offset: 0x0254 */
290 uint32_t gpio5b_ds_2; /* address offset: 0x0258 */
291 uint32_t gpio5b_ds_3; /* address offset: 0x025c */
292 uint32_t gpio5c_ds_0; /* address offset: 0x0260 */
293 uint32_t gpio5c_ds_1; /* address offset: 0x0264 */
294 uint32_t gpio5c_ds_2; /* address offset: 0x0268 */
295 uint32_t gpio5c_ds_3; /* address offset: 0x026c */
296 uint32_t gpio5d_ds_0; /* address offset: 0x0270 */
297 uint32_t gpio5d_ds_1; /* address offset: 0x0274 */
298 uint32_t gpio5d_ds_2; /* address offset: 0x0278 */
299 uint32_t gpio5d_ds_3; /* address offset: 0x027c */
300 uint32_t reserved0280[52]; /* address offset: 0x0280 */
301 uint32_t gpio5a_pull; /* address offset: 0x0350 */
302 uint32_t gpio5b_pull; /* address offset: 0x0354 */
303 uint32_t gpio5c_pull; /* address offset: 0x0358 */
304 uint32_t gpio5d_pull; /* address offset: 0x035c */
305 uint32_t reserved0360[60]; /* address offset: 0x0360 */
306 uint32_t gpio5a_ie; /* address offset: 0x0450 */
307 uint32_t gpio5b_ie; /* address offset: 0x0454 */
308 uint32_t gpio5c_ie; /* address offset: 0x0458 */
309 uint32_t gpio5d_ie; /* address offset: 0x045c */
310 uint32_t reserved0460[60]; /* address offset: 0x0460 */
311 uint32_t gpio5a_smt; /* address offset: 0x0550 */
312 uint32_t gpio5b_smt; /* address offset: 0x0554 */
313 uint32_t gpio5c_smt; /* address offset: 0x0558 */
314 uint32_t gpio5d_smt; /* address offset: 0x055c */
315 uint32_t reserved0560[60]; /* address offset: 0x0560 */
316 uint32_t gpio5a_sus; /* address offset: 0x0650 */
317 uint32_t gpio5b_sus; /* address offset: 0x0654 */
318 uint32_t gpio5c_sus; /* address offset: 0x0658 */
319 uint32_t gpio5d_sus; /* address offset: 0x065c */
320 uint32_t reserved0660[60]; /* address offset: 0x0660 */
321 uint32_t gpio5a_sl; /* address offset: 0x0750 */
322 uint32_t gpio5b_sl; /* address offset: 0x0754 */
323 uint32_t gpio5c_sl; /* address offset: 0x0758 */
324 uint32_t gpio5d_sl; /* address offset: 0x075c */
325 uint32_t reserved0760[60]; /* address offset: 0x0760 */
326 uint32_t gpio5a_od; /* address offset: 0x0850 */
327 uint32_t gpio5b_od; /* address offset: 0x0854 */
328 uint32_t gpio5c_od; /* address offset: 0x0858 */
329 uint32_t gpio5d_od; /* address offset: 0x085c */
330 uint32_t reserved0860[46]; /* address offset: 0x0860 */
331 uint32_t io_vsel; /* address offset: 0x0918 */
332 uint32_t reserved091c[159]; /* address offset: 0x091c */
333 uint32_t grf_vicif_m1_con; /* address offset: 0x0b98 */
334 uint32_t grf_vop_lcdc_con; /* address offset: 0x0b9c */
335 uint32_t reserved0ba0[2]; /* address offset: 0x0ba0 */
336 uint32_t grf_gmacio_m1_con0; /* address offset: 0x0ba8 */
337 uint32_t grf_gmacio_m1_con1; /* address offset: 0x0bac */
338 uint32_t grf_uart0_dly_con; /* address offset: 0x0bb0 */
339 uint32_t grf_uart_jtag_con; /* address offset: 0x0bb4 */
340 uint32_t reserved0bb8[34]; /* address offset: 0x0bb8 */
341 uint32_t grf_gpio5_filter_con0; /* address offset: 0x0c40 */
342 uint32_t grf_gpio5_filter_con1; /* address offset: 0x0c44 */
343 uint32_t grf_gpio5_filter_con2; /* address offset: 0x0c48 */
344 uint32_t grf_gpio5_filter_con3; /* address offset: 0x0c4c */
345 uint32_t grf_gpio5_filter_con4; /* address offset: 0x0c50 */
346 uint32_t grf_gpio5_filter_con5; /* address offset: 0x0c54 */
353 uint32_t reserved0000[48]; /* address offset: 0x0000 */
354 uint32_t gpio6a_iomux_sel_0; /* address offset: 0x00c0 */
355 uint32_t gpio6a_iomux_sel_1; /* address offset: 0x00c4 */
356 uint32_t gpio6b_iomux_sel_0; /* address offset: 0x00c8 */
357 uint32_t gpio6b_iomux_sel_1; /* address offset: 0x00cc */
358 uint32_t gpio6c_iomux_sel_0; /* address offset: 0x00d0 */
359 uint32_t reserved00d4[107]; /* address offset: 0x00d4 */
360 uint32_t gpio6a_ds_0; /* address offset: 0x0280 */
361 uint32_t gpio6a_ds_1; /* address offset: 0x0284 */
362 uint32_t gpio6a_ds_2; /* address offset: 0x0288 */
363 uint32_t gpio6a_ds_3; /* address offset: 0x028c */
364 uint32_t gpio6b_ds_0; /* address offset: 0x0290 */
365 uint32_t gpio6b_ds_1; /* address offset: 0x0294 */
366 uint32_t gpio6b_ds_2; /* address offset: 0x0298 */
367 uint32_t gpio6b_ds_3; /* address offset: 0x029c */
368 uint32_t gpio6c_ds_0; /* address offset: 0x02a0 */
369 uint32_t gpio6c_ds_1; /* address offset: 0x02a4 */
370 uint32_t reserved02a8[46]; /* address offset: 0x02a8 */
371 uint32_t gpio6a_pull; /* address offset: 0x0360 */
372 uint32_t gpio6b_pull; /* address offset: 0x0364 */
373 uint32_t gpio6c_pull; /* address offset: 0x0368 */
374 uint32_t reserved036c[61]; /* address offset: 0x036c */
375 uint32_t gpio6a_ie; /* address offset: 0x0460 */
376 uint32_t gpio6b_ie; /* address offset: 0x0464 */
377 uint32_t gpio6c_ie; /* address offset: 0x0468 */
378 uint32_t reserved046c[61]; /* address offset: 0x046c */
379 uint32_t gpio6a_smt; /* address offset: 0x0560 */
380 uint32_t gpio6b_smt; /* address offset: 0x0564 */
381 uint32_t gpio6c_smt; /* address offset: 0x0568 */
382 uint32_t reserved056c[61]; /* address offset: 0x056c */
383 uint32_t gpio6a_sus; /* address offset: 0x0660 */
384 uint32_t gpio6b_sus; /* address offset: 0x0664 */
385 uint32_t gpio6c_sus; /* address offset: 0x0668 */
386 uint32_t reserved066c[61]; /* address offset: 0x066c */
387 uint32_t gpio6a_sl; /* address offset: 0x0760 */
388 uint32_t gpio6b_sl; /* address offset: 0x0764 */
389 uint32_t gpio6c_sl; /* address offset: 0x0768 */
390 uint32_t reserved076c[61]; /* address offset: 0x076c */
391 uint32_t gpio6a_od; /* address offset: 0x0860 */
392 uint32_t gpio6b_od; /* address offset: 0x0864 */
393 uint32_t gpio6c_od; /* address offset: 0x0868 */
394 uint32_t reserved086c[44]; /* address offset: 0x086c */
395 uint32_t io_vsel; /* address offset: 0x091c */
396 uint32_t reserved0920[157]; /* address offset: 0x0920 */
397 uint32_t grf_vicif_m0_con; /* address offset: 0x0b94 */
398 uint32_t reserved0b98[2]; /* address offset: 0x0b98 */
399 uint32_t grf_gmacio_m0_con0; /* address offset: 0x0ba0 */
400 uint32_t grf_gmacio_m0_con1; /* address offset: 0x0ba4 */
401 uint32_t reserved0ba8[46]; /* address offset: 0x0ba8 */
402 uint32_t grf_gpio6_filter_con0; /* address offset: 0x0c60 */
403 uint32_t grf_gpio6_filter_con1; /* address offset: 0x0c64 */
404 uint32_t grf_gpio6_filter_con2; /* address offset: 0x0c68 */
405 uint32_t grf_gpio6_filter_con3; /* address offset: 0x0c6c */
406 uint32_t grf_gpio6_filter_con4; /* address offset: 0x0c70 */
407 uint32_t grf_gpio6_filter_con5; /* address offset: 0x0c74 */
414 uint32_t reserved0000[56]; /* address offset: 0x0000 */
415 uint32_t gpio7a_iomux_sel_0; /* address offset: 0x00e0 */
416 uint32_t gpio7a_iomux_sel_1; /* address offset: 0x00e4 */
417 uint32_t gpio7b_iomux_sel_0; /* address offset: 0x00e8 */
418 uint32_t reserved00ec[117]; /* address offset: 0x00ec */
419 uint32_t gpio7a_ds_0; /* address offset: 0x02c0 */
420 uint32_t gpio7a_ds_1; /* address offset: 0x02c4 */
421 uint32_t gpio7a_ds_2; /* address offset: 0x02c8 */
422 uint32_t gpio7a_ds_3; /* address offset: 0x02cc */
423 uint32_t gpio7b_ds_0; /* address offset: 0x02d0 */
424 uint32_t reserved02d4[39]; /* address offset: 0x02d4 */
425 uint32_t gpio7a_pull; /* address offset: 0x0370 */
426 uint32_t gpio7b_pull; /* address offset: 0x0374 */
427 uint32_t reserved0378[62]; /* address offset: 0x0378 */
428 uint32_t gpio7a_ie; /* address offset: 0x0470 */
429 uint32_t gpio7b_ie; /* address offset: 0x0474 */
430 uint32_t reserved0478[62]; /* address offset: 0x0478 */
431 uint32_t gpio7a_smt; /* address offset: 0x0570 */
432 uint32_t gpio7b_smt; /* address offset: 0x0574 */
433 uint32_t reserved0578[62]; /* address offset: 0x0578 */
434 uint32_t gpio7a_sus; /* address offset: 0x0670 */
435 uint32_t gpio7b_sus; /* address offset: 0x0674 */
436 uint32_t reserved0678[62]; /* address offset: 0x0678 */
437 uint32_t gpio7a_sl; /* address offset: 0x0770 */
438 uint32_t gpio7b_sl; /* address offset: 0x0774 */
439 uint32_t reserved0778[62]; /* address offset: 0x0778 */
440 uint32_t gpio7a_od; /* address offset: 0x0870 */
441 uint32_t gpio7b_od; /* address offset: 0x0874 */
442 uint32_t reserved0878[42]; /* address offset: 0x0878 */
443 uint32_t io_vsel; /* address offset: 0x0920 */
444 uint32_t reserved0924[215]; /* address offset: 0x0924 */
445 uint32_t grf_gpio7_filter_con0; /* address offset: 0x0c80 */
446 uint32_t grf_gpio7_filter_con1; /* address offset: 0x0c84 */
447 uint32_t grf_gpio7_filter_con2; /* address offset: 0x0c88 */
448 uint32_t grf_gpio7_filter_con3; /* address offset: 0x0c8c */
449 uint32_t grf_gpio7_filter_con4; /* address offset: 0x0c90 */
450 uint32_t grf_gpio7_filter_con5; /* address offset: 0x0c94 */
451 uint32_t reserved0c98[2]; /* address offset: 0x0c98 */
452 uint32_t grf_dsm_ioc_con; /* address offset: 0x0ca0 */