1*b9dcc643SXuhui Lin /* 2*b9dcc643SXuhui Lin * (C) Copyright 2024 Rockchip Electronics Co., Ltd. 3*b9dcc643SXuhui Lin * 4*b9dcc643SXuhui Lin * SPDX-License-Identifier: GPL-2.0+ 5*b9dcc643SXuhui Lin */ 6*b9dcc643SXuhui Lin #ifndef _ASM_ARCH_GRF_RV1103B_H 7*b9dcc643SXuhui Lin #define _ASM_ARCH_GRF_RV1103B_H 8*b9dcc643SXuhui Lin 9*b9dcc643SXuhui Lin #include <common.h> 10*b9dcc643SXuhui Lin 11*b9dcc643SXuhui Lin /* 12*b9dcc643SXuhui Lin * You can choose: 13*b9dcc643SXuhui Lin * (1) Directly use concrete grf reg, like struct rv1103b_cpu_grf_reg. 14*b9dcc643SXuhui Lin * (2) Add regs you need to struct rv1103b_grf, use rv1103b_grf directly. 15*b9dcc643SXuhui Lin */ 16*b9dcc643SXuhui Lin #define VEPU_GRF 0x20100000 17*b9dcc643SXuhui Lin #define NPU_GRF 0x20110000 18*b9dcc643SXuhui Lin #define VI_GRF 0x20120000 19*b9dcc643SXuhui Lin #define CPU_GRF 0x20130000 20*b9dcc643SXuhui Lin #define DDR_GRF 0x20140000 21*b9dcc643SXuhui Lin #define SYS_GRF 0x20150000 22*b9dcc643SXuhui Lin #define PMU_GRF 0x20160000 23*b9dcc643SXuhui Lin struct rv1103b_grf { 24*b9dcc643SXuhui Lin uint32_t reserved0[(SYS_GRF + 0xA0 - VEPU_GRF)/ 4]; 25*b9dcc643SXuhui Lin uint32_t gmac_con0; /* address offset: 0x00a0 */ 26*b9dcc643SXuhui Lin uint32_t gmac_clk_con; /* address offset: 0x00a4 */ 27*b9dcc643SXuhui Lin uint32_t gmac_st; /* address offset: 0x00a8 */ 28*b9dcc643SXuhui Lin uint32_t reserved00ac; /* address offset: 0x00ac */ 29*b9dcc643SXuhui Lin uint32_t macphy_con0; /* address offset: 0x00b0 */ 30*b9dcc643SXuhui Lin uint32_t macphy_con1; /* address offset: 0x00b4 */ 31*b9dcc643SXuhui Lin uint32_t reserved1[(PMU_GRF + 0x10000 - (SYS_GRF + 0xB4)) / 4]; 32*b9dcc643SXuhui Lin }; 33*b9dcc643SXuhui Lin 34*b9dcc643SXuhui Lin check_member(rv1103b_grf, macphy_con1, SYS_GRF + 0xB4 - VEPU_GRF); 35*b9dcc643SXuhui Lin 36*b9dcc643SXuhui Lin /* grf_cpu register structure define */ 37*b9dcc643SXuhui Lin struct rv1103b_cpu_grf_reg { 38*b9dcc643SXuhui Lin uint32_t con0; /* address offset: 0x0000 */ 39*b9dcc643SXuhui Lin uint32_t mem_cfg_uhdspra; /* address offset: 0x0004 */ 40*b9dcc643SXuhui Lin uint32_t status; /* address offset: 0x0008 */ 41*b9dcc643SXuhui Lin }; 42*b9dcc643SXuhui Lin 43*b9dcc643SXuhui Lin check_member(rv1103b_cpu_grf_reg, status, 0x0008); 44*b9dcc643SXuhui Lin 45*b9dcc643SXuhui Lin /* grf_ddr register structure define */ 46*b9dcc643SXuhui Lin struct rv1103b_ddr_grf_reg { 47*b9dcc643SXuhui Lin uint32_t con0; /* address offset: 0x0000 */ 48*b9dcc643SXuhui Lin uint32_t con1; /* address offset: 0x0004 */ 49*b9dcc643SXuhui Lin uint32_t con2; /* address offset: 0x0008 */ 50*b9dcc643SXuhui Lin uint32_t con3; /* address offset: 0x000c */ 51*b9dcc643SXuhui Lin uint32_t con4; /* address offset: 0x0010 */ 52*b9dcc643SXuhui Lin uint32_t con5; /* address offset: 0x0014 */ 53*b9dcc643SXuhui Lin uint32_t con6; /* address offset: 0x0018 */ 54*b9dcc643SXuhui Lin uint32_t con7; /* address offset: 0x001c */ 55*b9dcc643SXuhui Lin uint32_t con8; /* address offset: 0x0020 */ 56*b9dcc643SXuhui Lin uint32_t con9; /* address offset: 0x0024 */ 57*b9dcc643SXuhui Lin uint32_t con10; /* address offset: 0x0028 */ 58*b9dcc643SXuhui Lin uint32_t con11; /* address offset: 0x002c */ 59*b9dcc643SXuhui Lin uint32_t con12; /* address offset: 0x0030 */ 60*b9dcc643SXuhui Lin uint32_t con13; /* address offset: 0x0034 */ 61*b9dcc643SXuhui Lin uint32_t con14; /* address offset: 0x0038 */ 62*b9dcc643SXuhui Lin uint32_t reserved003c[17]; /* address offset: 0x003c */ 63*b9dcc643SXuhui Lin uint32_t probe_ctrl; /* address offset: 0x0080 */ 64*b9dcc643SXuhui Lin uint32_t reserved0084[39]; /* address offset: 0x0084 */ 65*b9dcc643SXuhui Lin uint32_t status8; /* address offset: 0x0120 */ 66*b9dcc643SXuhui Lin uint32_t status9; /* address offset: 0x0124 */ 67*b9dcc643SXuhui Lin }; 68*b9dcc643SXuhui Lin 69*b9dcc643SXuhui Lin check_member(rv1103b_ddr_grf_reg, status9, 0x0124); 70*b9dcc643SXuhui Lin 71*b9dcc643SXuhui Lin /* grf_npu register structure define */ 72*b9dcc643SXuhui Lin struct rv1103b_npu_grf_reg { 73*b9dcc643SXuhui Lin uint32_t mem_con_spra; /* address offset: 0x0000 */ 74*b9dcc643SXuhui Lin }; 75*b9dcc643SXuhui Lin 76*b9dcc643SXuhui Lin check_member(rv1103b_npu_grf_reg, mem_con_spra, 0x0000); 77*b9dcc643SXuhui Lin 78*b9dcc643SXuhui Lin /* grf_pmu register structure define */ 79*b9dcc643SXuhui Lin struct rv1103b_pmu_grf_reg { 80*b9dcc643SXuhui Lin uint32_t soc_con0; /* address offset: 0x0000 */ 81*b9dcc643SXuhui Lin uint32_t soc_con1; /* address offset: 0x0004 */ 82*b9dcc643SXuhui Lin uint32_t soc_con2; /* address offset: 0x0008 */ 83*b9dcc643SXuhui Lin uint32_t soc_con3; /* address offset: 0x000c */ 84*b9dcc643SXuhui Lin uint32_t soc_con4; /* address offset: 0x0010 */ 85*b9dcc643SXuhui Lin uint32_t soc_con5; /* address offset: 0x0014 */ 86*b9dcc643SXuhui Lin uint32_t soc_con6; /* address offset: 0x0018 */ 87*b9dcc643SXuhui Lin uint32_t soc_con7; /* address offset: 0x001c */ 88*b9dcc643SXuhui Lin uint32_t soc_con8; /* address offset: 0x0020 */ 89*b9dcc643SXuhui Lin uint32_t soc_con9; /* address offset: 0x0024 */ 90*b9dcc643SXuhui Lin uint32_t soc_con10; /* address offset: 0x0028 */ 91*b9dcc643SXuhui Lin uint32_t reserved002c; /* address offset: 0x002c */ 92*b9dcc643SXuhui Lin uint32_t soc_status0; /* address offset: 0x0030 */ 93*b9dcc643SXuhui Lin uint32_t reserved0034[3]; /* address offset: 0x0034 */ 94*b9dcc643SXuhui Lin uint32_t men_con; /* address offset: 0x0040 */ 95*b9dcc643SXuhui Lin uint32_t reserved0044[3]; /* address offset: 0x0044 */ 96*b9dcc643SXuhui Lin uint32_t soc_special0; /* address offset: 0x0050 */ 97*b9dcc643SXuhui Lin uint32_t reserved0054[3]; /* address offset: 0x0054 */ 98*b9dcc643SXuhui Lin uint32_t soc_preroll_int_con; /* address offset: 0x0060 */ 99*b9dcc643SXuhui Lin uint32_t reserved0064[103]; /* address offset: 0x0064 */ 100*b9dcc643SXuhui Lin uint32_t os_reg0; /* address offset: 0x0200 */ 101*b9dcc643SXuhui Lin uint32_t os_reg1; /* address offset: 0x0204 */ 102*b9dcc643SXuhui Lin uint32_t os_reg2; /* address offset: 0x0208 */ 103*b9dcc643SXuhui Lin uint32_t os_reg3; /* address offset: 0x020c */ 104*b9dcc643SXuhui Lin uint32_t os_reg4; /* address offset: 0x0210 */ 105*b9dcc643SXuhui Lin uint32_t os_reg5; /* address offset: 0x0214 */ 106*b9dcc643SXuhui Lin uint32_t os_reg6; /* address offset: 0x0218 */ 107*b9dcc643SXuhui Lin uint32_t os_reg7; /* address offset: 0x021c */ 108*b9dcc643SXuhui Lin uint32_t os_reg8; /* address offset: 0x0220 */ 109*b9dcc643SXuhui Lin uint32_t os_reg9; /* address offset: 0x0224 */ 110*b9dcc643SXuhui Lin uint32_t os_reg10; /* address offset: 0x0228 */ 111*b9dcc643SXuhui Lin uint32_t os_reg11; /* address offset: 0x022c */ 112*b9dcc643SXuhui Lin uint32_t reset_function_status; /* address offset: 0x0230 */ 113*b9dcc643SXuhui Lin uint32_t reset_function_clr; /* address offset: 0x0234 */ 114*b9dcc643SXuhui Lin }; 115*b9dcc643SXuhui Lin 116*b9dcc643SXuhui Lin check_member(rv1103b_pmu_grf_reg, reset_function_clr, 0x0234); 117*b9dcc643SXuhui Lin 118*b9dcc643SXuhui Lin /* grf_sys register structure define */ 119*b9dcc643SXuhui Lin struct rv1103b_sys_grf_reg { 120*b9dcc643SXuhui Lin uint32_t peri_con0; /* address offset: 0x0000 */ 121*b9dcc643SXuhui Lin uint32_t peri_con1; /* address offset: 0x0004 */ 122*b9dcc643SXuhui Lin uint32_t peri_con2; /* address offset: 0x0008 */ 123*b9dcc643SXuhui Lin uint32_t peri_hprot2_con; /* address offset: 0x000c */ 124*b9dcc643SXuhui Lin uint32_t peri_status; /* address offset: 0x0010 */ 125*b9dcc643SXuhui Lin uint32_t reserved0014[3]; /* address offset: 0x0014 */ 126*b9dcc643SXuhui Lin uint32_t audio_con0; /* address offset: 0x0020 */ 127*b9dcc643SXuhui Lin uint32_t audio_con1; /* address offset: 0x0024 */ 128*b9dcc643SXuhui Lin uint32_t reserved0028[2]; /* address offset: 0x0028 */ 129*b9dcc643SXuhui Lin uint32_t usbotg_con0; /* address offset: 0x0030 */ 130*b9dcc643SXuhui Lin uint32_t usbotg_con1; /* address offset: 0x0034 */ 131*b9dcc643SXuhui Lin uint32_t reserved0038[2]; /* address offset: 0x0038 */ 132*b9dcc643SXuhui Lin uint32_t usbotg_status0; /* address offset: 0x0040 */ 133*b9dcc643SXuhui Lin uint32_t usbotg_status1; /* address offset: 0x0044 */ 134*b9dcc643SXuhui Lin uint32_t usbotg_status2; /* address offset: 0x0048 */ 135*b9dcc643SXuhui Lin uint32_t reserved004c; /* address offset: 0x004c */ 136*b9dcc643SXuhui Lin uint32_t usbphy_con0; /* address offset: 0x0050 */ 137*b9dcc643SXuhui Lin uint32_t usbphy_con1; /* address offset: 0x0054 */ 138*b9dcc643SXuhui Lin uint32_t usbphy_con2; /* address offset: 0x0058 */ 139*b9dcc643SXuhui Lin uint32_t usbphy_con3; /* address offset: 0x005c */ 140*b9dcc643SXuhui Lin uint32_t usbphy_status; /* address offset: 0x0060 */ 141*b9dcc643SXuhui Lin uint32_t reserved0064[3]; /* address offset: 0x0064 */ 142*b9dcc643SXuhui Lin uint32_t saradc_con; /* address offset: 0x0070 */ 143*b9dcc643SXuhui Lin uint32_t tsadc_con; /* address offset: 0x0074 */ 144*b9dcc643SXuhui Lin uint32_t otp_con; /* address offset: 0x0078 */ 145*b9dcc643SXuhui Lin uint32_t reserved007c; /* address offset: 0x007c */ 146*b9dcc643SXuhui Lin uint32_t mem_con_spra; /* address offset: 0x0080 */ 147*b9dcc643SXuhui Lin uint32_t mem_con_dpra; /* address offset: 0x0084 */ 148*b9dcc643SXuhui Lin uint32_t mem_con_rom; /* address offset: 0x0088 */ 149*b9dcc643SXuhui Lin uint32_t mem_con_gate; /* address offset: 0x008c */ 150*b9dcc643SXuhui Lin uint32_t biu_con0; /* address offset: 0x0090 */ 151*b9dcc643SXuhui Lin uint32_t reserved0094; /* address offset: 0x0094 */ 152*b9dcc643SXuhui Lin uint32_t biu_status0; /* address offset: 0x0098 */ 153*b9dcc643SXuhui Lin uint32_t biu_status1; /* address offset: 0x009c */ 154*b9dcc643SXuhui Lin uint32_t gmac_con0; /* address offset: 0x00a0 */ 155*b9dcc643SXuhui Lin uint32_t gmac_clk_con; /* address offset: 0x00a4 */ 156*b9dcc643SXuhui Lin uint32_t gmac_st; /* address offset: 0x00a8 */ 157*b9dcc643SXuhui Lin uint32_t reserved00ac; /* address offset: 0x00ac */ 158*b9dcc643SXuhui Lin uint32_t macphy_con0; /* address offset: 0x00b0 */ 159*b9dcc643SXuhui Lin uint32_t macphy_con1; /* address offset: 0x00b4 */ 160*b9dcc643SXuhui Lin uint32_t reserved00b8[18]; /* address offset: 0x00b8 */ 161*b9dcc643SXuhui Lin uint32_t usbotg_sig_detect_con; /* address offset: 0x0100 */ 162*b9dcc643SXuhui Lin uint32_t usbotg_sig_detect_status; /* address offset: 0x0104 */ 163*b9dcc643SXuhui Lin uint32_t usbotg_sig_detect_clr; /* address offset: 0x0108 */ 164*b9dcc643SXuhui Lin uint32_t reserved010c; /* address offset: 0x010c */ 165*b9dcc643SXuhui Lin uint32_t usbotg_linestate_detect_con; /* address offset: 0x0110 */ 166*b9dcc643SXuhui Lin uint32_t usbotg_disconnect_detect_con; /* address offset: 0x0114 */ 167*b9dcc643SXuhui Lin uint32_t usbotg_bvalid_detect_con; /* address offset: 0x0118 */ 168*b9dcc643SXuhui Lin uint32_t usbotg_id_detect_con; /* address offset: 0x011c */ 169*b9dcc643SXuhui Lin uint32_t reserved0120[56]; /* address offset: 0x0120 */ 170*b9dcc643SXuhui Lin uint32_t cache_peri_addr_start; /* address offset: 0x0200 */ 171*b9dcc643SXuhui Lin uint32_t cache_peri_addr_end; /* address offset: 0x0204 */ 172*b9dcc643SXuhui Lin uint32_t hpmcu_code_addr_start; /* address offset: 0x0208 */ 173*b9dcc643SXuhui Lin uint32_t hpmcu_sram_addr_start; /* address offset: 0x020c */ 174*b9dcc643SXuhui Lin uint32_t hpmcu_exsram_addr_start; /* address offset: 0x0210 */ 175*b9dcc643SXuhui Lin uint32_t hpmcu_cache_misc; /* address offset: 0x0214 */ 176*b9dcc643SXuhui Lin uint32_t hpmcu_cache_status; /* address offset: 0x0218 */ 177*b9dcc643SXuhui Lin uint32_t reserved021c[377]; /* address offset: 0x021c */ 178*b9dcc643SXuhui Lin uint32_t chip_id; /* address offset: 0x0800 */ 179*b9dcc643SXuhui Lin uint32_t chip_version; /* address offset: 0x0804 */ 180*b9dcc643SXuhui Lin }; 181*b9dcc643SXuhui Lin 182*b9dcc643SXuhui Lin check_member(rv1103b_sys_grf_reg, chip_version, 0x0804); 183*b9dcc643SXuhui Lin 184*b9dcc643SXuhui Lin /* grf_vepu register structure define */ 185*b9dcc643SXuhui Lin struct rv1103b_vepu_grf_reg { 186*b9dcc643SXuhui Lin uint32_t mem_con_spra; /* address offset: 0x0000 */ 187*b9dcc643SXuhui Lin uint32_t mem_con_dpra; /* address offset: 0x0004 */ 188*b9dcc643SXuhui Lin }; 189*b9dcc643SXuhui Lin 190*b9dcc643SXuhui Lin check_member(rv1103b_vepu_grf_reg, mem_con_dpra, 0x0004); 191*b9dcc643SXuhui Lin 192*b9dcc643SXuhui Lin /* grf_vi register structure define */ 193*b9dcc643SXuhui Lin struct rv1103b_vi_grf_reg { 194*b9dcc643SXuhui Lin uint32_t mem_con_spra; /* address offset: 0x0000 */ 195*b9dcc643SXuhui Lin uint32_t mem_con_dpra; /* address offset: 0x0004 */ 196*b9dcc643SXuhui Lin uint32_t reserved0008; /* address offset: 0x0008 */ 197*b9dcc643SXuhui Lin uint32_t vi_hprot2_con; /* address offset: 0x000c */ 198*b9dcc643SXuhui Lin uint32_t status; /* address offset: 0x0010 */ 199*b9dcc643SXuhui Lin uint32_t csiphy_con; /* address offset: 0x0014 */ 200*b9dcc643SXuhui Lin uint32_t csiphy_status; /* address offset: 0x0018 */ 201*b9dcc643SXuhui Lin uint32_t reserved001c; /* address offset: 0x001c */ 202*b9dcc643SXuhui Lin uint32_t misc_con; /* address offset: 0x0020 */ 203*b9dcc643SXuhui Lin uint32_t sdmmc_det_cnt; /* address offset: 0x0024 */ 204*b9dcc643SXuhui Lin uint32_t sdmmc_sig_detect_con; /* address offset: 0x0028 */ 205*b9dcc643SXuhui Lin uint32_t sdmmc_sig_detect_status; /* address offset: 0x002c */ 206*b9dcc643SXuhui Lin uint32_t sdmmc_status_clr; /* address offset: 0x0030 */ 207*b9dcc643SXuhui Lin }; 208*b9dcc643SXuhui Lin 209*b9dcc643SXuhui Lin check_member(rv1103b_vi_grf_reg, sdmmc_status_clr, 0x0030); 210*b9dcc643SXuhui Lin 211*b9dcc643SXuhui Lin #endif /* _ASM_ARCH_GRF_RV1103B_H */ 212