Lines Matching refs:uint32_t
12 uint32_t reserved0[0x40018 / 4];
15 uint32_t gmac1_con0; /* Address Offset: 0x40018 */
16 uint32_t gmac1_con1; /* Address Offset: 0x4001c */
17 uint32_t reserved1[(0x60018 - 0x4001c) / 4 - 1];
20 uint32_t gmac0_con; /* Address Offset: 0x60018 */
21 uint32_t macphy_con0; /* Address Offset: 0x6001c */
22 uint32_t macphy_con1; /* Address Offset: 0x60020 */
23 uint32_t sdmmc_con0; /* Address Offset: 0x60024 */
24 uint32_t sdmmc_con1; /* Address Offset: 0x60028 */
25 uint32_t reserved2[(0x70000 - 0x60028) / 4 - 1];
28 uint32_t soc_con[8]; /* Address Offset: 0x70000 */
29 uint32_t soc_status; /* Address Offset: 0x70020 */
30 uint32_t reserved3[3]; /* Address Offset: 0x70024 */
31 uint32_t pmuio_vsel; /* Address Offset: 0x70030 */
32 uint32_t reserved4[3]; /* Address Offset: 0x70034 */
33 uint32_t mem_con; /* Address Offset: 0x70040 */
34 uint32_t reserved5[47]; /* Address Offset: 0x70044 */
35 uint32_t rstfunc_status; /* Address Offset: 0x70100 */
36 uint32_t rstfunc_clr; /* Address Offset: 0x70104 */
37 uint32_t reserved6[62]; /* Address Offset: 0x70108 */
38 uint32_t os_reg0; /* Address Offset: 0x70200 */
39 uint32_t os_reg1; /* Address Offset: 0x70204 */
40 uint32_t os_reg2; /* Address Offset: 0x70208 */
41 uint32_t os_reg3; /* Address Offset: 0x7020C */
42 uint32_t os_reg4; /* Address Offset: 0x70210 */
43 uint32_t os_reg5; /* Address Offset: 0x70214 */
44 uint32_t os_reg6; /* Address Offset: 0x70218 */
45 uint32_t os_reg7; /* Address Offset: 0x7021C */
46 uint32_t os_reg8; /* Address Offset: 0x70220 */
47 uint32_t os_reg9; /* Address Offset: 0x70224 */
48 uint32_t os_reg10; /* Address Offset: 0x70228 */
49 uint32_t os_reg11; /* Address Offset: 0x7022C */
50 uint32_t os_reg12; /* Address Offset: 0x70230 */
51 uint32_t os_reg13; /* Address Offset: 0x70234 */
52 uint32_t os_reg14; /* Address Offset: 0x70238 */
53 uint32_t os_reg15; /* Address Offset: 0x7023C */
54 uint32_t os_reg16; /* Address Offset: 0x70240 */
55 uint32_t os_reg17; /* Address Offset: 0x70244 */
56 uint32_t os_reg18; /* Address Offset: 0x70248 */
57 uint32_t os_reg19; /* Address Offset: 0x7024C */
58 uint32_t os_reg20; /* Address Offset: 0x70250 */
59 uint32_t os_reg21; /* Address Offset: 0x70254 */
60 uint32_t os_reg22; /* Address Offset: 0x70258 */
61 uint32_t os_reg23; /* Address Offset: 0x7025C */
62 uint32_t reserved7[(0x80000 - 0x7025C) / 4 - 1];
64 uint32_t grf_sys_con[2]; /* Address Offset: 0x80000 */
65 uint32_t reserved8[2]; /* Address Offset: 0x80008 */
66 uint32_t grf_sys_status; /* Address Offset: 0x80010 */
67 uint32_t reserved9[3]; /* Address Offset: 0x80014 */
68 uint32_t grf_biu_con[2]; /* Address Offset: 0x80020 */
69 uint32_t reserved10[2]; /* Address Offset: 0x80028 */
70 uint32_t grf_biu_status[3]; /* Address Offset: 0x80030 */
71 uint32_t reserved11[17]; /* Address Offset: 0x8003C */
72 uint32_t grf_sys_mem_con[5]; /* Address Offset: 0x80080 */
73 uint32_t reserved12[59]; /* Address Offset: 0x80094 */
74 uint32_t grf_soc_code; /* Address Offset: 0x80180 */
75 uint32_t reserved13[3]; /* Address Offset: 0x80184 */
76 uint32_t grf_soc_version; /* Address Offset: 0x80190 */
77 uint32_t reserved14[3]; /* Address Offset: 0x80194 */
78 uint32_t grf_chip_id; /* Address Offset: 0x801A0 */
79 uint32_t reserved15[3]; /* Address Offset: 0x801A4 */
80 uint32_t grf_chip_version; /* Address Offset: 0x801B0 */
81 uint32_t reserved16[(0x10000 - 0x81b0) / 4 - 1];