1*85e5c210SXuhui Lin /* 2*85e5c210SXuhui Lin * (C) Copyright 2023 Rockchip Electronics Co., Ltd. 3*85e5c210SXuhui Lin * 4*85e5c210SXuhui Lin * SPDX-License-Identifier: GPL-2.0+ 5*85e5c210SXuhui Lin */ 6*85e5c210SXuhui Lin #ifndef _ASM_ARCH_GRF_RK3506_H 7*85e5c210SXuhui Lin #define _ASM_ARCH_GRF_RK3506_H 8*85e5c210SXuhui Lin 9*85e5c210SXuhui Lin #include <common.h> 10*85e5c210SXuhui Lin 11*85e5c210SXuhui Lin /* grf register structure define */ 12*85e5c210SXuhui Lin struct rk3506_grf_reg { 13*85e5c210SXuhui Lin uint32_t soc_con0; /* address offset: 0x0000 */ 14*85e5c210SXuhui Lin uint32_t soc_con1; /* address offset: 0x0004 */ 15*85e5c210SXuhui Lin uint32_t soc_con2; /* address offset: 0x0008 */ 16*85e5c210SXuhui Lin uint32_t soc_con3; /* address offset: 0x000c */ 17*85e5c210SXuhui Lin uint32_t soc_con4; /* address offset: 0x0010 */ 18*85e5c210SXuhui Lin uint32_t soc_con5; /* address offset: 0x0014 */ 19*85e5c210SXuhui Lin uint32_t soc_con6; /* address offset: 0x0018 */ 20*85e5c210SXuhui Lin uint32_t soc_con7; /* address offset: 0x001c */ 21*85e5c210SXuhui Lin uint32_t soc_con8; /* address offset: 0x0020 */ 22*85e5c210SXuhui Lin uint32_t soc_con9; /* address offset: 0x0024 */ 23*85e5c210SXuhui Lin uint32_t soc_con10; /* address offset: 0x0028 */ 24*85e5c210SXuhui Lin uint32_t soc_con11; /* address offset: 0x002c */ 25*85e5c210SXuhui Lin uint32_t reserved0030; /* address offset: 0x0030 */ 26*85e5c210SXuhui Lin uint32_t soc_con13; /* address offset: 0x0034 */ 27*85e5c210SXuhui Lin uint32_t soc_con14; /* address offset: 0x0038 */ 28*85e5c210SXuhui Lin uint32_t soc_con15; /* address offset: 0x003c */ 29*85e5c210SXuhui Lin uint32_t soc_con16; /* address offset: 0x0040 */ 30*85e5c210SXuhui Lin uint32_t soc_con17; /* address offset: 0x0044 */ 31*85e5c210SXuhui Lin uint32_t soc_con18; /* address offset: 0x0048 */ 32*85e5c210SXuhui Lin uint32_t soc_con19; /* address offset: 0x004c */ 33*85e5c210SXuhui Lin uint32_t soc_con20; /* address offset: 0x0050 */ 34*85e5c210SXuhui Lin uint32_t soc_con21; /* address offset: 0x0054 */ 35*85e5c210SXuhui Lin uint32_t soc_con22; /* address offset: 0x0058 */ 36*85e5c210SXuhui Lin uint32_t soc_con23; /* address offset: 0x005c */ 37*85e5c210SXuhui Lin uint32_t soc_con24; /* address offset: 0x0060 */ 38*85e5c210SXuhui Lin uint32_t soc_con25; /* address offset: 0x0064 */ 39*85e5c210SXuhui Lin uint32_t soc_con26; /* address offset: 0x0068 */ 40*85e5c210SXuhui Lin uint32_t soc_con27; /* address offset: 0x006c */ 41*85e5c210SXuhui Lin uint32_t soc_con28; /* address offset: 0x0070 */ 42*85e5c210SXuhui Lin uint32_t soc_con29; /* address offset: 0x0074 */ 43*85e5c210SXuhui Lin uint32_t soc_con30; /* address offset: 0x0078 */ 44*85e5c210SXuhui Lin uint32_t soc_con31; /* address offset: 0x007c */ 45*85e5c210SXuhui Lin uint32_t soc_con32; /* address offset: 0x0080 */ 46*85e5c210SXuhui Lin uint32_t soc_con33; /* address offset: 0x0084 */ 47*85e5c210SXuhui Lin uint32_t reserved0088; /* address offset: 0x0088 */ 48*85e5c210SXuhui Lin uint32_t soc_con35; /* address offset: 0x008c */ 49*85e5c210SXuhui Lin uint32_t soc_con36; /* address offset: 0x0090 */ 50*85e5c210SXuhui Lin uint32_t soc_con37; /* address offset: 0x0094 */ 51*85e5c210SXuhui Lin uint32_t soc_con38; /* address offset: 0x0098 */ 52*85e5c210SXuhui Lin uint32_t soc_con39; /* address offset: 0x009c */ 53*85e5c210SXuhui Lin uint32_t soc_con40; /* address offset: 0x00a0 */ 54*85e5c210SXuhui Lin uint32_t soc_con41; /* address offset: 0x00a4 */ 55*85e5c210SXuhui Lin uint32_t soc_con42; /* address offset: 0x00a8 */ 56*85e5c210SXuhui Lin uint32_t soc_con43; /* address offset: 0x00ac */ 57*85e5c210SXuhui Lin uint32_t reserved00b0[20]; /* address offset: 0x00b0 */ 58*85e5c210SXuhui Lin uint32_t soc_status0; /* address offset: 0x0100 */ 59*85e5c210SXuhui Lin uint32_t soc_status1; /* address offset: 0x0104 */ 60*85e5c210SXuhui Lin uint32_t soc_status2; /* address offset: 0x0108 */ 61*85e5c210SXuhui Lin uint32_t reserved010c; /* address offset: 0x010c */ 62*85e5c210SXuhui Lin uint32_t ddr_status0; /* address offset: 0x0110 */ 63*85e5c210SXuhui Lin uint32_t ddr_status1; /* address offset: 0x0114 */ 64*85e5c210SXuhui Lin uint32_t usbphy_status; /* address offset: 0x0118 */ 65*85e5c210SXuhui Lin uint32_t reserved011c[13]; /* address offset: 0x011c */ 66*85e5c210SXuhui Lin uint32_t usbotg0_sig_detect_con; /* address offset: 0x0150 */ 67*85e5c210SXuhui Lin uint32_t usbotg0_sig_detect_status; /* address offset: 0x0154 */ 68*85e5c210SXuhui Lin uint32_t usbotg0_sig_detect_clr; /* address offset: 0x0158 */ 69*85e5c210SXuhui Lin uint32_t usbotg0_vbusvalid_detect_con; /* address offset: 0x015c */ 70*85e5c210SXuhui Lin uint32_t usbotg0_linestate_detect_con; /* address offset: 0x0160 */ 71*85e5c210SXuhui Lin uint32_t usbotg0_disconnect_detect_con; /* address offset: 0x0164 */ 72*85e5c210SXuhui Lin uint32_t usbotg0_bvalid_detect_con; /* address offset: 0x0168 */ 73*85e5c210SXuhui Lin uint32_t usbotg0_id_detect_con; /* address offset: 0x016c */ 74*85e5c210SXuhui Lin uint32_t usbotg1_sig_detect_con; /* address offset: 0x0170 */ 75*85e5c210SXuhui Lin uint32_t usbotg1_sig_detect_status; /* address offset: 0x0174 */ 76*85e5c210SXuhui Lin uint32_t usbotg1_sig_detect_clr; /* address offset: 0x0178 */ 77*85e5c210SXuhui Lin uint32_t usbotg1_vbusvalid_detect_con; /* address offset: 0x017c */ 78*85e5c210SXuhui Lin uint32_t usbotg1_linestate_detect_con; /* address offset: 0x0180 */ 79*85e5c210SXuhui Lin uint32_t usbotg1_disconnect_detect_con; /* address offset: 0x0184 */ 80*85e5c210SXuhui Lin uint32_t usbotg1_bvalid_detect_con; /* address offset: 0x0188 */ 81*85e5c210SXuhui Lin uint32_t usbotg1_id_detect_con; /* address offset: 0x018c */ 82*85e5c210SXuhui Lin uint32_t reserved0190[4]; /* address offset: 0x0190 */ 83*85e5c210SXuhui Lin uint32_t mac0_mcgr_ack; /* address offset: 0x01a0 */ 84*85e5c210SXuhui Lin uint32_t mac1_mcgr_ack; /* address offset: 0x01a4 */ 85*85e5c210SXuhui Lin uint32_t reserved01a8[22]; /* address offset: 0x01a8 */ 86*85e5c210SXuhui Lin uint32_t os_reg0; /* address offset: 0x0200 */ 87*85e5c210SXuhui Lin uint32_t os_reg1; /* address offset: 0x0204 */ 88*85e5c210SXuhui Lin uint32_t os_reg2; /* address offset: 0x0208 */ 89*85e5c210SXuhui Lin uint32_t os_reg3; /* address offset: 0x020c */ 90*85e5c210SXuhui Lin uint32_t os_reg4; /* address offset: 0x0210 */ 91*85e5c210SXuhui Lin uint32_t os_reg5; /* address offset: 0x0214 */ 92*85e5c210SXuhui Lin uint32_t os_reg6; /* address offset: 0x0218 */ 93*85e5c210SXuhui Lin uint32_t os_reg7; /* address offset: 0x021c */ 94*85e5c210SXuhui Lin uint32_t os_reg8; /* address offset: 0x0220 */ 95*85e5c210SXuhui Lin uint32_t os_reg9; /* address offset: 0x0224 */ 96*85e5c210SXuhui Lin uint32_t os_reg10; /* address offset: 0x0228 */ 97*85e5c210SXuhui Lin uint32_t os_reg11; /* address offset: 0x022c */ 98*85e5c210SXuhui Lin uint32_t reserved0230[52]; /* address offset: 0x0230 */ 99*85e5c210SXuhui Lin uint32_t soc_version; /* address offset: 0x0300 */ 100*85e5c210SXuhui Lin }; 101*85e5c210SXuhui Lin 102*85e5c210SXuhui Lin check_member(rk3506_grf_reg, soc_version, 0x0300); 103*85e5c210SXuhui Lin 104*85e5c210SXuhui Lin /* grf_core register structure define */ 105*85e5c210SXuhui Lin struct rk3506_grf_core_reg { 106*85e5c210SXuhui Lin uint32_t pvtpll_con0_l; /* address offset: 0x0000 */ 107*85e5c210SXuhui Lin uint32_t pvtpll_con0_h; /* address offset: 0x0004 */ 108*85e5c210SXuhui Lin uint32_t pvtpll_con1; /* address offset: 0x0008 */ 109*85e5c210SXuhui Lin uint32_t pvtpll_con2; /* address offset: 0x000c */ 110*85e5c210SXuhui Lin uint32_t pvtpll_con3; /* address offset: 0x0010 */ 111*85e5c210SXuhui Lin uint32_t pvtpll_osc_cnt; /* address offset: 0x0014 */ 112*85e5c210SXuhui Lin uint32_t pvtpll_osc_cnt_avg; /* address offset: 0x0018 */ 113*85e5c210SXuhui Lin uint32_t reserved001c[17]; /* address offset: 0x001c */ 114*85e5c210SXuhui Lin uint32_t cpu_status; /* address offset: 0x0060 */ 115*85e5c210SXuhui Lin uint32_t cpu_con0; /* address offset: 0x0064 */ 116*85e5c210SXuhui Lin uint32_t cpu_con1; /* address offset: 0x0068 */ 117*85e5c210SXuhui Lin uint32_t cpu_mem_con0; /* address offset: 0x006c */ 118*85e5c210SXuhui Lin uint32_t reserved0070[5]; /* address offset: 0x0070 */ 119*85e5c210SXuhui Lin uint32_t soc_con0; /* address offset: 0x0084 */ 120*85e5c210SXuhui Lin uint32_t soc_con1; /* address offset: 0x0088 */ 121*85e5c210SXuhui Lin uint32_t soc_con2; /* address offset: 0x008c */ 122*85e5c210SXuhui Lin uint32_t soc_con3; /* address offset: 0x0090 */ 123*85e5c210SXuhui Lin uint32_t soc_con4; /* address offset: 0x0094 */ 124*85e5c210SXuhui Lin uint32_t soc_con5; /* address offset: 0x0098 */ 125*85e5c210SXuhui Lin }; 126*85e5c210SXuhui Lin 127*85e5c210SXuhui Lin check_member(rk3506_grf_core_reg, soc_con5, 0x0098); 128*85e5c210SXuhui Lin 129*85e5c210SXuhui Lin /* grf_pmu register structure define */ 130*85e5c210SXuhui Lin struct rk3506_grf_pmu_reg { 131*85e5c210SXuhui Lin uint32_t soc_con0; /* address offset: 0x0000 */ 132*85e5c210SXuhui Lin uint32_t soc_con1; /* address offset: 0x0004 */ 133*85e5c210SXuhui Lin uint32_t soc_con2; /* address offset: 0x0008 */ 134*85e5c210SXuhui Lin uint32_t soc_con3; /* address offset: 0x000c */ 135*85e5c210SXuhui Lin uint32_t soc_con4; /* address offset: 0x0010 */ 136*85e5c210SXuhui Lin uint32_t soc_con5; /* address offset: 0x0014 */ 137*85e5c210SXuhui Lin uint32_t soc_con6; /* address offset: 0x0018 */ 138*85e5c210SXuhui Lin uint32_t soc_con7; /* address offset: 0x001c */ 139*85e5c210SXuhui Lin uint32_t soc_con8; /* address offset: 0x0020 */ 140*85e5c210SXuhui Lin uint32_t soc_con9; /* address offset: 0x0024 */ 141*85e5c210SXuhui Lin uint32_t soc_con10; /* address offset: 0x0028 */ 142*85e5c210SXuhui Lin uint32_t soc_con11; /* address offset: 0x002c */ 143*85e5c210SXuhui Lin uint32_t soc_con12; /* address offset: 0x0030 */ 144*85e5c210SXuhui Lin uint32_t soc_con13; /* address offset: 0x0034 */ 145*85e5c210SXuhui Lin uint32_t soc_con14; /* address offset: 0x0038 */ 146*85e5c210SXuhui Lin uint32_t soc_con15; /* address offset: 0x003c */ 147*85e5c210SXuhui Lin uint32_t soc_con16; /* address offset: 0x0040 */ 148*85e5c210SXuhui Lin uint32_t soc_con17; /* address offset: 0x0044 */ 149*85e5c210SXuhui Lin uint32_t soc_con18; /* address offset: 0x0048 */ 150*85e5c210SXuhui Lin uint32_t reserved004c[45]; /* address offset: 0x004c */ 151*85e5c210SXuhui Lin uint32_t soc_status; /* address offset: 0x0100 */ 152*85e5c210SXuhui Lin uint32_t reserved0104[63]; /* address offset: 0x0104 */ 153*85e5c210SXuhui Lin uint32_t os_reg0; /* address offset: 0x0200 */ 154*85e5c210SXuhui Lin uint32_t os_reg1; /* address offset: 0x0204 */ 155*85e5c210SXuhui Lin uint32_t os_reg2; /* address offset: 0x0208 */ 156*85e5c210SXuhui Lin uint32_t os_reg3; /* address offset: 0x020c */ 157*85e5c210SXuhui Lin uint32_t os_reg4; /* address offset: 0x0210 */ 158*85e5c210SXuhui Lin uint32_t os_reg5; /* address offset: 0x0214 */ 159*85e5c210SXuhui Lin uint32_t os_reg6; /* address offset: 0x0218 */ 160*85e5c210SXuhui Lin uint32_t os_reg7; /* address offset: 0x021c */ 161*85e5c210SXuhui Lin uint32_t os_reg8; /* address offset: 0x0220 */ 162*85e5c210SXuhui Lin uint32_t os_reg9; /* address offset: 0x0224 */ 163*85e5c210SXuhui Lin uint32_t os_reg10; /* address offset: 0x0228 */ 164*85e5c210SXuhui Lin uint32_t os_reg11; /* address offset: 0x022c */ 165*85e5c210SXuhui Lin uint32_t rstfunc_status; /* address offset: 0x0230 */ 166*85e5c210SXuhui Lin uint32_t rstfunc_clr; /* address offset: 0x0234 */ 167*85e5c210SXuhui Lin uint32_t reserved0238[882]; /* address offset: 0x0238 */ 168*85e5c210SXuhui Lin uint32_t mcu_iso_con0; /* address offset: 0x1000 */ 169*85e5c210SXuhui Lin uint32_t mcu_iso_con1; /* address offset: 0x1004 */ 170*85e5c210SXuhui Lin uint32_t mcu_iso_con2; /* address offset: 0x1008 */ 171*85e5c210SXuhui Lin uint32_t mcu_iso_con3; /* address offset: 0x100c */ 172*85e5c210SXuhui Lin uint32_t mcu_iso_con4; /* address offset: 0x1010 */ 173*85e5c210SXuhui Lin uint32_t mcu_iso_con5; /* address offset: 0x1014 */ 174*85e5c210SXuhui Lin uint32_t mcu_iso_con6; /* address offset: 0x1018 */ 175*85e5c210SXuhui Lin uint32_t mcu_iso_con7; /* address offset: 0x101c */ 176*85e5c210SXuhui Lin uint32_t mcu_iso_con8; /* address offset: 0x1020 */ 177*85e5c210SXuhui Lin uint32_t mcu_iso_con9; /* address offset: 0x1024 */ 178*85e5c210SXuhui Lin uint32_t mcu_iso_con10; /* address offset: 0x1028 */ 179*85e5c210SXuhui Lin uint32_t mcu_iso_con11; /* address offset: 0x102c */ 180*85e5c210SXuhui Lin uint32_t reserved1030[244]; /* address offset: 0x1030 */ 181*85e5c210SXuhui Lin uint32_t mcu_iso_ddr_con0; /* address offset: 0x1400 */ 182*85e5c210SXuhui Lin uint32_t mcu_iso_ddr_con1; /* address offset: 0x1404 */ 183*85e5c210SXuhui Lin uint32_t reserved1408[62]; /* address offset: 0x1408 */ 184*85e5c210SXuhui Lin uint32_t mcu_iso_lock; /* address offset: 0x1500 */ 185*85e5c210SXuhui Lin uint32_t reserved1504[703]; /* address offset: 0x1504 */ 186*85e5c210SXuhui Lin uint32_t cpu_iso_con0; /* address offset: 0x2000 */ 187*85e5c210SXuhui Lin uint32_t cpu_iso_con1; /* address offset: 0x2004 */ 188*85e5c210SXuhui Lin uint32_t cpu_iso_con2; /* address offset: 0x2008 */ 189*85e5c210SXuhui Lin uint32_t cpu_iso_con3; /* address offset: 0x200c */ 190*85e5c210SXuhui Lin uint32_t cpu_iso_con4; /* address offset: 0x2010 */ 191*85e5c210SXuhui Lin uint32_t cpu_iso_con5; /* address offset: 0x2014 */ 192*85e5c210SXuhui Lin uint32_t cpu_iso_con6; /* address offset: 0x2018 */ 193*85e5c210SXuhui Lin uint32_t cpu_iso_con7; /* address offset: 0x201c */ 194*85e5c210SXuhui Lin uint32_t cpu_iso_con8; /* address offset: 0x2020 */ 195*85e5c210SXuhui Lin uint32_t cpu_iso_con9; /* address offset: 0x2024 */ 196*85e5c210SXuhui Lin uint32_t cpu_iso_con10; /* address offset: 0x2028 */ 197*85e5c210SXuhui Lin uint32_t cpu_iso_con11; /* address offset: 0x202c */ 198*85e5c210SXuhui Lin uint32_t reserved2030[244]; /* address offset: 0x2030 */ 199*85e5c210SXuhui Lin uint32_t cpu_iso_ddr_con0; /* address offset: 0x2400 */ 200*85e5c210SXuhui Lin uint32_t cpu_iso_ddr_con1; /* address offset: 0x2404 */ 201*85e5c210SXuhui Lin uint32_t reserved2408[62]; /* address offset: 0x2408 */ 202*85e5c210SXuhui Lin uint32_t cpu_iso_lock; /* address offset: 0x2500 */ 203*85e5c210SXuhui Lin }; 204*85e5c210SXuhui Lin 205*85e5c210SXuhui Lin check_member(rk3506_grf_pmu_reg, cpu_iso_lock, 0x2500); 206*85e5c210SXuhui Lin 207*85e5c210SXuhui Lin #endif /* _ASM_ARCH_GRF_RK3506_H */ 208