Lines Matching refs:uint32_t
12 uint32_t reserved0000[3]; /* Address Offset: 0x0000 */
13 uint32_t gpio0b_iomux_sel_h; /* Address Offset: 0x000C */
14 uint32_t gpio0c_iomux_sel_l; /* Address Offset: 0x0010 */
15 uint32_t gpio0c_iomux_sel_h; /* Address Offset: 0x0014 */
16 uint32_t gpio0d_iomux_sel_l; /* Address Offset: 0x0018 */
17 uint32_t gpio0d_iomux_sel_h; /* Address Offset: 0x001C */
18 uint32_t gpio1a_iomux_sel_l; /* Address Offset: 0x0020 */
19 uint32_t gpio1a_iomux_sel_h; /* Address Offset: 0x0024 */
20 uint32_t gpio1b_iomux_sel_l; /* Address Offset: 0x0028 */
21 uint32_t gpio1b_iomux_sel_h; /* Address Offset: 0x002C */
22 uint32_t gpio1c_iomux_sel_l; /* Address Offset: 0x0030 */
23 uint32_t gpio1c_iomux_sel_h; /* Address Offset: 0x0034 */
24 uint32_t gpio1d_iomux_sel_l; /* Address Offset: 0x0038 */
25 uint32_t gpio1d_iomux_sel_h; /* Address Offset: 0x003C */
26 uint32_t gpio2a_iomux_sel_l; /* Address Offset: 0x0040 */
27 uint32_t gpio2a_iomux_sel_h; /* Address Offset: 0x0044 */
28 uint32_t gpio2b_iomux_sel_l; /* Address Offset: 0x0048 */
29 uint32_t gpio2b_iomux_sel_h; /* Address Offset: 0x004C */
30 uint32_t gpio2c_iomux_sel_l; /* Address Offset: 0x0050 */
31 uint32_t gpio2c_iomux_sel_h; /* Address Offset: 0x0054 */
32 uint32_t gpio2d_iomux_sel_l; /* Address Offset: 0x0058 */
33 uint32_t gpio2d_iomux_sel_h; /* Address Offset: 0x005C */
34 uint32_t gpio3a_iomux_sel_l; /* Address Offset: 0x0060 */
35 uint32_t gpio3a_iomux_sel_h; /* Address Offset: 0x0064 */
36 uint32_t gpio3b_iomux_sel_l; /* Address Offset: 0x0068 */
37 uint32_t gpio3b_iomux_sel_h; /* Address Offset: 0x006C */
38 uint32_t gpio3c_iomux_sel_l; /* Address Offset: 0x0070 */
39 uint32_t gpio3c_iomux_sel_h; /* Address Offset: 0x0074 */
40 uint32_t gpio3d_iomux_sel_l; /* Address Offset: 0x0078 */
41 uint32_t gpio3d_iomux_sel_h; /* Address Offset: 0x007C */
42 uint32_t gpio4a_iomux_sel_l; /* Address Offset: 0x0080 */
43 uint32_t gpio4a_iomux_sel_h; /* Address Offset: 0x0084 */
44 uint32_t gpio4b_iomux_sel_l; /* Address Offset: 0x0088 */
45 uint32_t gpio4b_iomux_sel_h; /* Address Offset: 0x008C */
46 uint32_t gpio4c_iomux_sel_l; /* Address Offset: 0x0090 */
47 uint32_t gpio4c_iomux_sel_h; /* Address Offset: 0x0094 */
48 uint32_t gpio4d_iomux_sel_l; /* Address Offset: 0x0098 */
49 uint32_t gpio4d_iomux_sel_h; /* Address Offset: 0x009C */
55 uint32_t gpio0a_iomux_sel_l; /* Address Offset: 0x0000 */
56 uint32_t gpio0a_iomux_sel_h; /* Address Offset: 0x0004 */
57 uint32_t gpio0b_iomux_sel_l; /* Address Offset: 0x0008 */
58 uint32_t reserved0012; /* Address Offset: 0x000C */
59 uint32_t gpio0a_ds_l; /* Address Offset: 0x0010 */
60 uint32_t gpio0a_ds_h; /* Address Offset: 0x0014 */
61 uint32_t gpio0b_ds_l; /* Address Offset: 0x0018 */
62 uint32_t reserved0028; /* Address Offset: 0x001C */
63 uint32_t gpio0a_p; /* Address Offset: 0x0020 */
64 uint32_t gpio0b_p; /* Address Offset: 0x0024 */
65 uint32_t gpio0a_ie; /* Address Offset: 0x0028 */
66 uint32_t gpio0b_ie; /* Address Offset: 0x002C */
67 uint32_t gpio0a_smt; /* Address Offset: 0x0030 */
68 uint32_t gpio0b_smt; /* Address Offset: 0x0034 */
69 uint32_t gpio0a_pdis; /* Address Offset: 0x0038 */
70 uint32_t gpio0b_pdis; /* Address Offset: 0x003C */
71 uint32_t xin_con; /* Address Offset: 0x0040 */
76 uint32_t gpio0b_iomux_sel_h; /* Address Offset: 0x0000 */
77 uint32_t gpio0c_iomux_sel_l; /* Address Offset: 0x0004 */
78 uint32_t gpio0c_iomux_sel_h; /* Address Offset: 0x0008 */
79 uint32_t gpio0d_iomux_sel_l; /* Address Offset: 0x000C */
80 uint32_t gpio0d_iomux_sel_h; /* Address Offset: 0x0010 */
81 uint32_t gpio0b_ds_h; /* Address Offset: 0x0014 */
82 uint32_t gpio0c_ds_l; /* Address Offset: 0x0018 */
83 uint32_t gpio0c_ds_h; /* Address Offset: 0x001C */
84 uint32_t gpio0d_ds_l; /* Address Offset: 0x0020 */
85 uint32_t gpio0d_ds_h; /* Address Offset: 0x0024 */
86 uint32_t gpio0b_p; /* Address Offset: 0x0028 */
87 uint32_t gpio0c_p; /* Address Offset: 0x002C */
88 uint32_t gpio0d_p; /* Address Offset: 0x0030 */
89 uint32_t gpio0b_ie; /* Address Offset: 0x0034 */
90 uint32_t gpio0c_ie; /* Address Offset: 0x0038 */
91 uint32_t gpio0d_ie; /* Address Offset: 0x003C */
92 uint32_t gpio0b_smt; /* Address Offset: 0x0040 */
93 uint32_t gpio0c_smt; /* Address Offset: 0x0044 */
94 uint32_t gpio0d_smt; /* Address Offset: 0x0048 */
95 uint32_t gpio0b_pdis; /* Address Offset: 0x004C */
96 uint32_t gpio0c_pdis; /* Address Offset: 0x0050 */
97 uint32_t gpio0d_pdis; /* Address Offset: 0x0054 */